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tcg/sparc64: Allocate %g2 as a third temporary

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-04-24 02:38:03 -05:00
parent 3df73c7e39
commit 33982b890b
1 changed files with 7 additions and 8 deletions
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15
tcg/sparc64/tcg-target.c.inc
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@ -83,9 +83,10 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
#define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) #define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
/* Define some temporary registers. T2 is used for constant generation. */ /* Define some temporary registers. T3 is used for constant generation. */
#define TCG_REG_T1 TCG_REG_G1 #define TCG_REG_T1 TCG_REG_G1
#define TCG_REG_T2 TCG_REG_O7 #define TCG_REG_T2 TCG_REG_G2
#define TCG_REG_T3 TCG_REG_O7
#ifndef CONFIG_SOFTMMU #ifndef CONFIG_SOFTMMU
# define TCG_GUEST_BASE_REG TCG_REG_I5 # define TCG_GUEST_BASE_REG TCG_REG_I5
@ -110,7 +111,6 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_I4, TCG_REG_I4,
TCG_REG_I5, TCG_REG_I5,
TCG_REG_G2,
TCG_REG_G3, TCG_REG_G3,
TCG_REG_G4, TCG_REG_G4,
TCG_REG_G5, TCG_REG_G5,
@ -492,8 +492,8 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
static void tcg_out_movi(TCGContext *s, TCGType type, static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg) TCGReg ret, tcg_target_long arg)
{ {
tcg_debug_assert(ret != TCG_REG_T2); tcg_debug_assert(ret != TCG_REG_T3);
tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2); tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T3);
} }
static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
@ -885,10 +885,8 @@ static void tcg_out_jmpl_const(TCGContext *s, const tcg_insn_unit *dest,
{ {
uintptr_t desti = (uintptr_t)dest; uintptr_t desti = (uintptr_t)dest;
/* Be careful not to clobber %o7 for a tail call. */
tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1,
desti & ~0xfff, in_prologue, desti & ~0xfff, in_prologue, TCG_REG_T2);
tail_call ? TCG_REG_G2 : TCG_REG_O7);
tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7, tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7,
TCG_REG_T1, desti & 0xfff, JMPL); TCG_REG_T1, desti & 0xfff, JMPL);
} }
@ -1856,6 +1854,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_T3); /* for internal use */
} }
#define ELF_HOST_MACHINE EM_SPARCV9 #define ELF_HOST_MACHINE EM_SPARCV9