target/arm: Remove log2_esize parameter to gen_mte_checkN
The log2_esize parameter is not used except trivially. Drop the parameter and the deferral to gen_mte_check1. This fixes a bug in that the parameters as documented in the header file were the reverse from those in the implementation. Which meant that translate-sve.c was passing the parameters in the wrong order. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210416183106.1516563-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -295,9 +295,9 @@ TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
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* For MTE, check multiple logical sequential accesses.
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*/
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TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
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bool tag_checked, int log2_esize, int total_size)
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bool tag_checked, int size)
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{
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if (tag_checked && s->mte_active[0] && total_size != (1 << log2_esize)) {
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if (tag_checked && s->mte_active[0]) {
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TCGv_i32 tcg_desc;
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TCGv_i64 ret;
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int desc = 0;
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@ -306,7 +306,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
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desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
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desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
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desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
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desc = FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1);
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desc = FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1);
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tcg_desc = tcg_const_i32(desc);
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ret = new_tmp_a64(s);
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@ -315,7 +315,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
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return ret;
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}
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return gen_mte_check1(s, addr, is_write, tag_checked, log2_esize);
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return clean_data_tbi(s, addr);
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}
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typedef struct DisasCompare64 {
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@ -2965,8 +2965,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
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}
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clean_addr = gen_mte_checkN(s, dirty_addr, !is_load,
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(wback || rn != 31) && !set_tag,
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size, 2 << size);
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(wback || rn != 31) && !set_tag, 2 << size);
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if (is_vector) {
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if (is_load) {
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@ -3713,7 +3712,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
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* promote consecutive little-endian elements below.
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*/
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clean_addr = gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != 31,
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size, total);
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total);
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/*
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* Consecutive little-endian elements from a single register
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@ -3866,7 +3865,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
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tcg_rn = cpu_reg_sp(s, rn);
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clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31,
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scale, total);
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total);
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tcg_ebytes = tcg_const_i64(1 << scale);
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for (xs = 0; xs < selem; xs++) {
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@ -44,7 +44,7 @@ TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
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TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
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bool tag_checked, int log2_size);
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TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
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bool tag_checked, int count, int log2_esize);
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bool tag_checked, int size);
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/* We should have at some point before trying to access an FP register
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* done the necessary access check, so assert that
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@ -4264,7 +4264,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
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dirty_addr = tcg_temp_new_i64();
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tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm);
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clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len, MO_8);
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clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len);
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tcg_temp_free_i64(dirty_addr);
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/*
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@ -4352,7 +4352,7 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
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dirty_addr = tcg_temp_new_i64();
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tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm);
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clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len, MO_8);
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clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len);
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tcg_temp_free_i64(dirty_addr);
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/* Note that unpredicated load/store of vector/predicate registers
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