added PIIX3 like IDE controller - PCI irq generation - SETFEATURES IDE command support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@852 c046a42c-6fe2-441c-8c8c-71466251a162
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bellard
parent
9995c51ffd
commit
34e538ae5d
93
hw/ide.c
93
hw/ide.c
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@ -297,6 +297,7 @@ typedef struct IDEState {
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int64_t nb_sectors;
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int mult_sectors;
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int irq;
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PCIDevice *pci_dev;
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int drive_serial;
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/* ide regs */
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uint8_t feature;
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@ -463,7 +464,10 @@ static inline void ide_abort_command(IDEState *s)
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static inline void ide_set_irq(IDEState *s)
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{
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if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
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pic_set_irq(s->irq, 1);
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if (s->irq == 16)
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pci_set_irq(s->pci_dev, 0, 1);
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else
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pic_set_irq(s->irq, 1);
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}
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}
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@ -1169,7 +1173,22 @@ static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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s->status = READY_STAT;
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ide_set_irq(s);
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break;
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case WIN_SETFEATURES:
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if (!s->bs)
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goto abort_cmd;
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/* XXX: valid for CDROM ? */
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switch(s->feature) {
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case 0x02: /* write cache enable */
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case 0x82: /* write cache disable */
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case 0xaa: /* read look-ahead enable */
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case 0x55: /* read look-ahead disable */
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s->status = READY_STAT;
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ide_set_irq(s);
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break;
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default:
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goto abort_cmd;
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}
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break;
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/* ATAPI commands */
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case WIN_PIDENTIFY:
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if (s->is_cdrom) {
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@ -1262,7 +1281,10 @@ static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
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ret = 0;
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else
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ret = s->status;
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pic_set_irq(s->irq, 0);
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if (s->irq == 16)
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pci_set_irq(s->pci_dev, 0, 0);
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else
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pic_set_irq(s->irq, 0);
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break;
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}
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#ifdef DEBUG_IDE
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@ -1481,6 +1503,22 @@ static void ide_init2(IDEState *ide_state, int irq,
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}
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}
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static void ide_init_ioport(IDEState *ide_state, int iobase, int iobase2)
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{
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register_ioport_write(iobase, 8, 1, ide_ioport_write, ide_state);
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register_ioport_read(iobase, 8, 1, ide_ioport_read, ide_state);
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if (iobase2) {
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register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state);
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register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state);
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}
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/* data ports */
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register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state);
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register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state);
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register_ioport_write(iobase, 4, 4, ide_data_writel, ide_state);
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register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state);
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}
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/***********************************************************/
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/* ISA IDE definitions */
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@ -1494,19 +1532,7 @@ void isa_ide_init(int iobase, int iobase2, int irq,
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return;
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ide_init2(ide_state, irq, hd0, hd1);
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register_ioport_write(iobase, 8, 1, ide_ioport_write, ide_state);
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register_ioport_read(iobase, 8, 1, ide_ioport_read, ide_state);
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if (iobase2) {
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register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state);
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register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state);
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}
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/* data ports */
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register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state);
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register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state);
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register_ioport_write(iobase, 4, 4, ide_data_writel, ide_state);
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register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state);
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ide_init_ioport(ide_state, iobase, iobase2);
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}
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/***********************************************************/
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@ -1546,7 +1572,8 @@ void pci_ide_init(BlockDriverState **hd_table)
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{
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PCIIDEState *d;
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uint8_t *pci_conf;
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int i;
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d = (PCIIDEState *)pci_register_device("IDE", sizeof(PCIIDEState),
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0, -1,
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NULL, NULL);
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@ -1573,6 +1600,38 @@ void pci_ide_init(BlockDriverState **hd_table)
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pci_register_io_region((PCIDevice *)d, 3, 0x4,
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PCI_ADDRESS_SPACE_IO, ide_map);
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pci_conf[0x3d] = 0x01; // interrupt on pin 1
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for(i = 0; i < 4; i++)
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d->ide_if[i].pci_dev = (PCIDevice *)d;
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ide_init2(&d->ide_if[0], 16, hd_table[0], hd_table[1]);
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ide_init2(&d->ide_if[2], 16, hd_table[2], hd_table[3]);
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}
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/* hd_table must contain 4 block drivers */
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/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
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void pci_piix3_ide_init(BlockDriverState **hd_table)
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{
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PCIIDEState *d;
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uint8_t *pci_conf;
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/* register a function 1 of PIIX3 */
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d = (PCIIDEState *)pci_register_device("PIIX3 IDE", sizeof(PCIIDEState),
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0, ((PCIDevice *)piix3_state)->devfn + 1,
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NULL, NULL);
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pci_conf = d->dev.config;
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pci_conf[0x00] = 0x86; // Intel
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pci_conf[0x01] = 0x80;
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pci_conf[0x02] = 0x10;
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pci_conf[0x03] = 0x70;
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pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
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pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
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pci_conf[0x0e] = 0x00; // header_type
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/* XXX: must add BMDMA support to be fully compliant */
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ide_init2(&d->ide_if[0], 14, hd_table[0], hd_table[1]);
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ide_init2(&d->ide_if[2], 15, hd_table[2], hd_table[3]);
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ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
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ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
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}
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