target-mips: Fix incorrect code and test for INSV
Content of register rs should be shifted for pos before applying a mask. This change contains both fix for the instruction and to the existing test. Signed-off-by: Petar Jovanovic <petarj@mips.com> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \
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\
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\
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filter = ((int32_t)0x01 << size) - 1; \
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filter = ((int32_t)0x01 << size) - 1; \
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filter = filter << pos; \
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filter = filter << pos; \
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temprs = rs & filter; \
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temprs = (rs << pos) & filter; \
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temprt = rt & ~filter; \
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temprt = rt & ~filter; \
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temp = temprs | temprt; \
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temp = temprs | temprt; \
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\
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\
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@ -10,7 +10,7 @@ int main()
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dsp = 0x305;
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dsp = 0x305;
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rt = 0x12345678;
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rt = 0x12345678;
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rs = 0x87654321;
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rs = 0x87654321;
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result = 0x12345338;
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result = 0x12345438;
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__asm
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__asm
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("wrdsp %2, 0x03\n\t"
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("wrdsp %2, 0x03\n\t"
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"insv %0, %1\n\t"
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"insv %0, %1\n\t"
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