target/i386: Introduce structures for mmu_translate
Create TranslateParams for inputs, TranslateResults for successful outputs, and TranslateFault for error outputs; return true on success. Move stage1 error paths from handle_mmu_fault to x86_cpu_tlb_fill; reorg the rest of handle_mmu_fault into get_physical_address. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221002172956.265735-4-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Richard Henderson
Paolo Bonzini
parent
e4ddff5262
commit
3563362ddf
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@ -22,30 +22,45 @@
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#include "exec/exec-all.h"
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#include "tcg/helper-tcg.h"
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#define PG_ERROR_OK (-1)
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typedef struct TranslateParams {
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target_ulong addr;
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target_ulong cr3;
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int pg_mode;
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int mmu_idx;
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MMUAccessType access_type;
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bool use_stage2;
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} TranslateParams;
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typedef struct TranslateResult {
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hwaddr paddr;
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int prot;
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int page_size;
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} TranslateResult;
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typedef struct TranslateFault {
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int exception_index;
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int error_code;
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target_ulong cr2;
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} TranslateFault;
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#define GET_HPHYS(cs, gpa, access_type, prot) \
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(use_stage2 ? get_hphys(cs, gpa, access_type, prot) : gpa)
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(in->use_stage2 ? get_hphys(cs, gpa, access_type, prot) : gpa)
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static int mmu_translate(CPUState *cs, hwaddr addr, bool use_stage2,
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uint64_t cr3, MMUAccessType access_type,
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int mmu_idx, int pg_mode,
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hwaddr *xlat, int *page_size, int *prot)
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static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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TranslateResult *out, TranslateFault *err)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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CPUState *cs = env_cpu(env);
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X86CPU *cpu = env_archcpu(env);
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const int32_t a20_mask = x86_get_a20_mask(env);
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const target_ulong addr = in->addr;
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const int pg_mode = in->pg_mode;
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const bool is_user = (in->mmu_idx == MMU_USER_IDX);
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const MMUAccessType access_type = in->access_type;
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uint64_t ptep, pte;
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int32_t a20_mask;
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target_ulong pde_addr, pte_addr;
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int error_code = 0;
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bool is_dirty, is_write, is_user;
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hwaddr pde_addr, pte_addr;
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uint64_t rsvd_mask = PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys_bits);
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uint32_t page_offset;
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uint32_t pkr;
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is_user = (mmu_idx == MMU_USER_IDX);
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is_write = (access_type == MMU_DATA_STORE);
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a20_mask = x86_get_a20_mask(env);
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int page_size;
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if (!(pg_mode & PG_MODE_NXE)) {
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rsvd_mask |= PG_NX_MASK;
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@ -62,7 +77,7 @@ static int mmu_translate(CPUState *cs, hwaddr addr, bool use_stage2,
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uint64_t pml4e_addr, pml4e;
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if (la57) {
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pml5e_addr = ((cr3 & ~0xfff) +
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pml5e_addr = ((in->cr3 & ~0xfff) +
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(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
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pml5e_addr = GET_HPHYS(cs, pml5e_addr, MMU_DATA_STORE, NULL);
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pml5e = x86_ldq_phys(cs, pml5e_addr);
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@ -78,7 +93,7 @@ static int mmu_translate(CPUState *cs, hwaddr addr, bool use_stage2,
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}
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ptep = pml5e ^ PG_NX_MASK;
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} else {
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pml5e = cr3;
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pml5e = in->cr3;
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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}
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@ -114,7 +129,7 @@ static int mmu_translate(CPUState *cs, hwaddr addr, bool use_stage2,
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}
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if (pdpe & PG_PSE_MASK) {
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/* 1 GB page */
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*page_size = 1024 * 1024 * 1024;
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page_size = 1024 * 1024 * 1024;
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pte_addr = pdpe_addr;
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pte = pdpe;
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goto do_check_protect;
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@ -123,7 +138,7 @@ static int mmu_translate(CPUState *cs, hwaddr addr, bool use_stage2,
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#endif
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{
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/* XXX: load them when cr3 is loaded ? */
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pdpe_addr = ((cr3 & ~0x1f) + ((addr >> 27) & 0x18)) &
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pdpe_addr = ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) &
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a20_mask;
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pdpe_addr = GET_HPHYS(cs, pdpe_addr, MMU_DATA_STORE, NULL);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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@ -150,7 +165,7 @@ static int mmu_translate(CPUState *cs, hwaddr addr, bool use_stage2,
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ptep &= pde ^ PG_NX_MASK;
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if (pde & PG_PSE_MASK) {
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/* 2 MB page */
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*page_size = 2048 * 1024;
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page_size = 2048 * 1024;
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pte_addr = pde_addr;
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pte = pde;
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goto do_check_protect;
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@ -172,12 +187,12 @@ static int mmu_translate(CPUState *cs, hwaddr addr, bool use_stage2,
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}
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/* combine pde and pte nx, user and rw protections */
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ptep &= pte ^ PG_NX_MASK;
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*page_size = 4096;
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page_size = 4096;
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} else {
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uint32_t pde;
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/* page directory entry */
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pde_addr = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) &
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pde_addr = ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) &
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a20_mask;
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pde_addr = GET_HPHYS(cs, pde_addr, MMU_DATA_STORE, NULL);
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pde = x86_ldl_phys(cs, pde_addr);
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@ -188,7 +203,7 @@ static int mmu_translate(CPUState *cs, hwaddr addr, bool use_stage2,
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/* if PSE bit is set, then we use a 4MB page */
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if ((pde & PG_PSE_MASK) && (pg_mode & PG_MODE_PSE)) {
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*page_size = 4096 * 1024;
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page_size = 4096 * 1024;
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pte_addr = pde_addr;
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/* Bits 20-13 provide bits 39-32 of the address, bit 21 is reserved.
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@ -214,12 +229,12 @@ static int mmu_translate(CPUState *cs, hwaddr addr, bool use_stage2,
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}
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/* combine pde and pte user and rw protections */
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ptep &= pte | PG_NX_MASK;
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*page_size = 4096;
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page_size = 4096;
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rsvd_mask = 0;
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}
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do_check_protect:
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rsvd_mask |= (*page_size - 1) & PG_ADDRESS_MASK & ~PG_PSE_PAT_MASK;
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rsvd_mask |= (page_size - 1) & PG_ADDRESS_MASK & ~PG_PSE_PAT_MASK;
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do_check_protect_pse36:
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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@ -231,17 +246,17 @@ do_check_protect_pse36:
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goto do_fault_protect;
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}
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*prot = 0;
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if (mmu_idx != MMU_KSMAP_IDX || !(ptep & PG_USER_MASK)) {
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*prot |= PAGE_READ;
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int prot = 0;
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if (in->mmu_idx != MMU_KSMAP_IDX || !(ptep & PG_USER_MASK)) {
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prot |= PAGE_READ;
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if ((ptep & PG_RW_MASK) || !(is_user || (pg_mode & PG_MODE_WP))) {
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*prot |= PAGE_WRITE;
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prot |= PAGE_WRITE;
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}
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}
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if (!(ptep & PG_NX_MASK) &&
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(mmu_idx == MMU_USER_IDX ||
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(is_user ||
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!((pg_mode & PG_MODE_SMEP) && (ptep & PG_USER_MASK)))) {
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*prot |= PAGE_EXEC;
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prot |= PAGE_EXEC;
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}
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if (ptep & PG_USER_MASK) {
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@ -260,164 +275,151 @@ do_check_protect_pse36:
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} else if (pkr_wd && (is_user || (pg_mode & PG_MODE_WP))) {
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pkr_prot &= ~PAGE_WRITE;
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}
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*prot &= pkr_prot;
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if ((pkr_prot & (1 << access_type)) == 0) {
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assert(access_type != MMU_INST_FETCH);
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error_code |= PG_ERROR_PK_MASK;
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goto do_fault_protect;
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goto do_fault_pk_protect;
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}
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prot &= pkr_prot;
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}
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if ((*prot & (1 << access_type)) == 0) {
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if ((prot & (1 << access_type)) == 0) {
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goto do_fault_protect;
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}
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/* yes, it can! */
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is_dirty = is_write && !(pte & PG_DIRTY_MASK);
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if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
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pte |= PG_ACCESSED_MASK;
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if (is_dirty) {
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pte |= PG_DIRTY_MASK;
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{
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uint32_t set = PG_ACCESSED_MASK;
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if (access_type == MMU_DATA_STORE) {
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set |= PG_DIRTY_MASK;
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}
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if (set & ~pte) {
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pte |= set;
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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if (!(pte & PG_DIRTY_MASK)) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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assert(!is_write);
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*prot &= ~PAGE_WRITE;
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assert(access_type != MMU_DATA_STORE);
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prot &= ~PAGE_WRITE;
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}
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pte = pte & a20_mask;
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out->prot = prot;
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out->page_size = page_size;
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/* align to page_size */
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pte &= PG_ADDRESS_MASK & ~(*page_size - 1);
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page_offset = addr & (*page_size - 1);
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*xlat = GET_HPHYS(cs, pte + page_offset, access_type, prot);
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return PG_ERROR_OK;
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out->paddr = (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1))
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| (addr & (page_size - 1));
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out->paddr = GET_HPHYS(cs, out->paddr, access_type, &out->prot);
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return true;
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int error_code;
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do_fault_rsvd:
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error_code |= PG_ERROR_RSVD_MASK;
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error_code = PG_ERROR_RSVD_MASK;
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goto do_fault_cont;
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do_fault_protect:
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error_code |= PG_ERROR_P_MASK;
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error_code = PG_ERROR_P_MASK;
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goto do_fault_cont;
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do_fault_pk_protect:
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assert(access_type != MMU_INST_FETCH);
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error_code = PG_ERROR_PK_MASK | PG_ERROR_P_MASK;
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goto do_fault_cont;
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do_fault:
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error_code |= (is_write << PG_ERROR_W_BIT);
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if (is_user)
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error_code = 0;
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do_fault_cont:
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if (is_user) {
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error_code |= PG_ERROR_U_MASK;
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if (access_type == MMU_INST_FETCH &&
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((pg_mode & PG_MODE_NXE) || (pg_mode & PG_MODE_SMEP)))
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error_code |= PG_ERROR_I_D_MASK;
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return error_code;
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}
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switch (access_type) {
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case MMU_DATA_LOAD:
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break;
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case MMU_DATA_STORE:
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error_code |= PG_ERROR_W_MASK;
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break;
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case MMU_INST_FETCH:
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if (pg_mode & (PG_MODE_NXE | PG_MODE_SMEP)) {
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error_code |= PG_ERROR_I_D_MASK;
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}
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break;
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}
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err->exception_index = EXCP0E_PAGE;
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err->error_code = error_code;
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err->cr2 = addr;
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return false;
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}
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hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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int *prot)
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int *prot)
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{
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CPUX86State *env = &X86_CPU(cs)->env;
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uint64_t exit_info_1;
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int page_size;
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int next_prot;
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hwaddr hphys;
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if (likely(!(env->hflags2 & HF2_NPT_MASK))) {
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return gphys;
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}
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} else {
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TranslateParams in = {
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.addr = gphys,
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.cr3 = env->nested_cr3,
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.pg_mode = env->nested_pg_mode,
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.mmu_idx = MMU_USER_IDX,
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.access_type = access_type,
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.use_stage2 = false,
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};
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TranslateResult out;
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TranslateFault err;
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uint64_t exit_info_1;
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exit_info_1 = mmu_translate(cs, gphys, false, env->nested_cr3,
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access_type, MMU_USER_IDX, env->nested_pg_mode,
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&hphys, &page_size, &next_prot);
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if (exit_info_1 == PG_ERROR_OK) {
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if (prot) {
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*prot &= next_prot;
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if (mmu_translate(env, &in, &out, &err)) {
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if (prot) {
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*prot &= out.prot;
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}
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return out.paddr;
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}
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return hphys;
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}
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x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
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gphys);
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if (prot) {
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exit_info_1 |= SVM_NPTEXIT_GPA;
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} else { /* page table access */
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exit_info_1 |= SVM_NPTEXIT_GPT;
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x86_stq_phys(cs, env->vm_vmcb +
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offsetof(struct vmcb, control.exit_info_2), gphys);
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exit_info_1 = err.error_code
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| (prot ? SVM_NPTEXIT_GPA : SVM_NPTEXIT_GPT);
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cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, env->retaddr);
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}
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cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, env->retaddr);
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}
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/* return value:
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* -1 = cannot handle fault
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* 0 = nothing more to do
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* 1 = generate PF fault
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*/
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static int handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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MMUAccessType access_type, int mmu_idx)
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static bool get_physical_address(CPUX86State *env, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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TranslateResult *out, TranslateFault *err)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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int error_code = PG_ERROR_OK;
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int pg_mode, prot, page_size;
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int32_t a20_mask;
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hwaddr paddr;
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hwaddr vaddr;
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#if defined(DEBUG_MMU)
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printf("MMU fault: addr=%" VADDR_PRIx " w=%d mmu=%d eip=" TARGET_FMT_lx "\n",
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addr, access_type, mmu_idx, env->eip);
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#endif
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if (!(env->cr[0] & CR0_PG_MASK)) {
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a20_mask = x86_get_a20_mask(env);
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paddr = addr & a20_mask;
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out->paddr = addr & x86_get_a20_mask(env);
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#ifdef TARGET_X86_64
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if (!(env->hflags & HF_LMA_MASK)) {
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/* Without long mode we can only address 32bits in real mode */
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paddr = (uint32_t)paddr;
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out->paddr = (uint32_t)out->paddr;
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}
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#endif
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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page_size = 4096;
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out->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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out->page_size = TARGET_PAGE_SIZE;
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return true;
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} else {
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pg_mode = get_pg_mode(env);
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if (pg_mode & PG_MODE_LMA) {
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int32_t sext;
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TranslateParams in = {
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.addr = addr,
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.cr3 = env->cr[3],
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.pg_mode = get_pg_mode(env),
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.mmu_idx = mmu_idx,
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.access_type = access_type,
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.use_stage2 = true
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};
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if (in.pg_mode & PG_MODE_LMA) {
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/* test virtual address sign extension */
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sext = (int64_t)addr >> (pg_mode & PG_MODE_LA57 ? 56 : 47);
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int shift = in.pg_mode & PG_MODE_LA57 ? 56 : 47;
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int64_t sext = (int64_t)addr >> shift;
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if (sext != 0 && sext != -1) {
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env->error_code = 0;
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cs->exception_index = EXCP0D_GPF;
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return 1;
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err->exception_index = EXCP0D_GPF;
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err->error_code = 0;
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err->cr2 = addr;
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return false;
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}
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}
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error_code = mmu_translate(cs, addr, true, env->cr[3], access_type,
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mmu_idx, pg_mode,
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&paddr, &page_size, &prot);
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}
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if (error_code == PG_ERROR_OK) {
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/* Even if 4MB pages, we map only one 4KB page in the cache to
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avoid filling it too fast */
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vaddr = addr & TARGET_PAGE_MASK;
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paddr &= TARGET_PAGE_MASK;
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assert(prot & (1 << access_type));
|
||||
tlb_set_page_with_attrs(cs, vaddr, paddr, cpu_get_mem_attrs(env),
|
||||
prot, mmu_idx, page_size);
|
||||
return 0;
|
||||
} else {
|
||||
if (env->intercept_exceptions & (1 << EXCP0E_PAGE)) {
|
||||
/* cr2 is not modified in case of exceptions */
|
||||
x86_stq_phys(cs,
|
||||
env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
|
||||
addr);
|
||||
} else {
|
||||
env->cr[2] = addr;
|
||||
}
|
||||
env->error_code = error_code;
|
||||
cs->exception_index = EXCP0E_PAGE;
|
||||
return 1;
|
||||
return mmu_translate(env, &in, out, err);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -425,17 +427,35 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
|
|||
MMUAccessType access_type, int mmu_idx,
|
||||
bool probe, uintptr_t retaddr)
|
||||
{
|
||||
X86CPU *cpu = X86_CPU(cs);
|
||||
CPUX86State *env = &cpu->env;
|
||||
CPUX86State *env = cs->env_ptr;
|
||||
TranslateResult out;
|
||||
TranslateFault err;
|
||||
|
||||
env->retaddr = retaddr;
|
||||
if (handle_mmu_fault(cs, addr, size, access_type, mmu_idx)) {
|
||||
/* FIXME: On error in get_hphys we have already jumped out. */
|
||||
g_assert(!probe);
|
||||
raise_exception_err_ra(env, cs->exception_index,
|
||||
env->error_code, retaddr);
|
||||
if (get_physical_address(env, addr, access_type, mmu_idx, &out, &err)) {
|
||||
/*
|
||||
* Even if 4MB pages, we map only one 4KB page in the cache to
|
||||
* avoid filling it too fast.
|
||||
*/
|
||||
assert(out.prot & (1 << access_type));
|
||||
tlb_set_page_with_attrs(cs, addr & TARGET_PAGE_MASK,
|
||||
out.paddr & TARGET_PAGE_MASK,
|
||||
cpu_get_mem_attrs(env),
|
||||
out.prot, mmu_idx, out.page_size);
|
||||
return true;
|
||||
}
|
||||
return true;
|
||||
|
||||
/* FIXME: On error in get_hphys we have already jumped out. */
|
||||
g_assert(!probe);
|
||||
|
||||
if (env->intercept_exceptions & (1 << err.exception_index)) {
|
||||
/* cr2 is not modified in case of exceptions */
|
||||
x86_stq_phys(cs, env->vm_vmcb +
|
||||
offsetof(struct vmcb, control.exit_info_2),
|
||||
err.cr2);
|
||||
} else {
|
||||
env->cr[2] = err.cr2;
|
||||
}
|
||||
raise_exception_err_ra(env, err.exception_index, err.error_code, retaddr);
|
||||
}
|
||||
|
||||
G_NORETURN void x86_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
|
||||
|
|
|
|||
Loading…
Reference in New Issue