aspeed/soc : Add AST1030 support
The embedded core of AST1030 SoC is ARM Coretex M4. It is hard to be integrated in the common Aspeed Soc framework. We introduce a new ast1030 class with instance_init and realize handlers. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: rename aspeed_ast10xx.c to aspeed_ast10x0.c to match zephyr ] Message-Id: <20220401083850.15266-8-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Steven Lee
Cédric Le Goater
parent
fa541a60dd
commit
356b230ed1
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@ -0,0 +1,299 @@
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/*
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* ASPEED Ast10x0 SoC
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*
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* Copyright (C) 2022 ASPEED Technology Inc.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*
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* Implementation extracted from the AST2600 and adapted for Ast10x0.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "hw/qdev-clock.h"
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#include "hw/misc/unimp.h"
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#include "hw/char/serial.h"
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#include "hw/arm/aspeed_soc.h"
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#define ASPEED_SOC_IOMEM_SIZE 0x00200000
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static const hwaddr aspeed_soc_ast1030_memmap[] = {
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[ASPEED_DEV_SRAM] = 0x00000000,
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[ASPEED_DEV_SBC] = 0x79000000,
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[ASPEED_DEV_IOMEM] = 0x7E600000,
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[ASPEED_DEV_PWM] = 0x7E610000,
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[ASPEED_DEV_FMC] = 0x7E620000,
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[ASPEED_DEV_SPI1] = 0x7E630000,
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[ASPEED_DEV_SPI2] = 0x7E640000,
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[ASPEED_DEV_SCU] = 0x7E6E2000,
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[ASPEED_DEV_ADC] = 0x7E6E9000,
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[ASPEED_DEV_SBC] = 0x7E6F2000,
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[ASPEED_DEV_GPIO] = 0x7E780000,
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[ASPEED_DEV_TIMER1] = 0x7E782000,
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[ASPEED_DEV_UART5] = 0x7E784000,
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[ASPEED_DEV_WDT] = 0x7E785000,
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[ASPEED_DEV_LPC] = 0x7E789000,
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[ASPEED_DEV_I2C] = 0x7E7B0000,
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};
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static const int aspeed_soc_ast1030_irqmap[] = {
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[ASPEED_DEV_UART5] = 8,
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[ASPEED_DEV_GPIO] = 11,
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[ASPEED_DEV_TIMER1] = 16,
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[ASPEED_DEV_TIMER2] = 17,
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[ASPEED_DEV_TIMER3] = 18,
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[ASPEED_DEV_TIMER4] = 19,
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[ASPEED_DEV_TIMER5] = 20,
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[ASPEED_DEV_TIMER6] = 21,
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[ASPEED_DEV_TIMER7] = 22,
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[ASPEED_DEV_TIMER8] = 23,
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[ASPEED_DEV_WDT] = 24,
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[ASPEED_DEV_LPC] = 35,
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[ASPEED_DEV_FMC] = 39,
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[ASPEED_DEV_PWM] = 44,
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[ASPEED_DEV_ADC] = 46,
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[ASPEED_DEV_SPI1] = 65,
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[ASPEED_DEV_SPI2] = 66,
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[ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
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[ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
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};
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static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[ctrl]);
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}
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static void aspeed_soc_ast1030_init(Object *obj)
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{
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AspeedSoCState *s = ASPEED_SOC(obj);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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char socname[8];
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char typename[64];
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int i;
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if (sscanf(sc->name, "%7s", socname) != 1) {
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g_assert_not_reached();
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}
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object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
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s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
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snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
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object_initialize_child(obj, "scu", &s->scu, typename);
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qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
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object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
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object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
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snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
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object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
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snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
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object_initialize_child(obj, "adc", &s->adc, typename);
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snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
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object_initialize_child(obj, "fmc", &s->fmc, typename);
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for (i = 0; i < sc->spis_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
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object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
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}
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object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
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object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
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for (i = 0; i < sc->wdts_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
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object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
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}
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}
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static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
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{
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AspeedSoCState *s = ASPEED_SOC(dev_soc);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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MemoryRegion *system_memory = get_system_memory();
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DeviceState *armv7m;
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Error *err = NULL;
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int i;
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if (!clock_has_source(s->sysclk)) {
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error_setg(errp, "sysclk clock must be wired up by the board code");
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return;
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}
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/* General I/O memory space to catch all unimplemented device */
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create_unimplemented_device("aspeed.sbc",
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sc->memmap[ASPEED_DEV_SBC],
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0x40000);
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create_unimplemented_device("aspeed.io",
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sc->memmap[ASPEED_DEV_IOMEM],
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ASPEED_SOC_IOMEM_SIZE);
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/* AST1030 CPU Core */
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armv7m = DEVICE(&s->armv7m);
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qdev_prop_set_uint32(armv7m, "num-irq", 256);
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qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
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qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
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object_property_set_link(OBJECT(&s->armv7m), "memory",
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OBJECT(system_memory), &error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
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/* Internal SRAM */
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memory_region_init_ram(&s->sram, NULL, "aspeed.sram", sc->sram_size, &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(system_memory,
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sc->memmap[ASPEED_DEV_SRAM],
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&s->sram);
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/* SCU */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
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/* LPC */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
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/* Connect the LPC IRQ to the GIC. It is otherwise unused. */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
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/*
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* On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
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*/
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
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qdev_get_gpio_in(DEVICE(&s->armv7m),
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sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
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qdev_get_gpio_in(DEVICE(&s->armv7m),
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sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
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qdev_get_gpio_in(DEVICE(&s->armv7m),
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sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
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qdev_get_gpio_in(DEVICE(&s->armv7m),
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sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
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/* UART5 - attach an 8250 to the IO space as our UART */
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serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
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aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
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38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
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/* Timer */
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object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
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sc->memmap[ASPEED_DEV_TIMER1]);
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for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
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qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
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}
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/* ADC */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
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/* FMC, The number of CS is set at the board level */
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object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
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ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
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/* SPI */
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for (i = 0; i < sc->spis_num; i++) {
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object_property_set_link(OBJECT(&s->spi[i]), "dram",
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OBJECT(&s->sram), &error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
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sc->memmap[ASPEED_DEV_SPI1 + i]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
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ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
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}
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/* Secure Boot Controller */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
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/* Watch dog */
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for (i = 0; i < sc->wdts_num; i++) {
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AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
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object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
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sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
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}
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}
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static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
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dc->realize = aspeed_soc_ast1030_realize;
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sc->name = "ast1030-a1";
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sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
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sc->silicon_rev = AST1030_A1_SILICON_REV;
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sc->sram_size = 0xc0000;
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sc->spis_num = 2;
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sc->ehcis_num = 0;
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sc->wdts_num = 4;
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sc->macs_num = 1;
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sc->irqmap = aspeed_soc_ast1030_irqmap;
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sc->memmap = aspeed_soc_ast1030_memmap;
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sc->num_cpus = 1;
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}
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static const TypeInfo aspeed_soc_ast1030_type_info = {
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.name = "ast1030-a1",
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.parent = TYPE_ASPEED_SOC,
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.instance_size = sizeof(AspeedSoCState),
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.instance_init = aspeed_soc_ast1030_init,
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.class_init = aspeed_soc_ast1030_class_init,
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.class_size = sizeof(AspeedSoCClass),
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};
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static void aspeed_soc_register_types(void)
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{
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type_register_static(&aspeed_soc_ast1030_type_info);
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}
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type_init(aspeed_soc_register_types)
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@ -47,7 +47,11 @@ arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-ver
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arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
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arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
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arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
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arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_soc.c', 'aspeed.c', 'aspeed_ast2600.c'))
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arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
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'aspeed_soc.c',
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'aspeed.c',
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'aspeed_ast2600.c',
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'aspeed_ast10x0.c'))
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arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
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arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
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arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
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@ -13,6 +13,7 @@
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#define ASPEED_SOC_H
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#include "hw/cpu/a15mpcore.h"
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#include "hw/arm/armv7m.h"
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#include "hw/intc/aspeed_vic.h"
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#include "hw/misc/aspeed_scu.h"
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#include "hw/adc/aspeed_adc.h"
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@ -47,6 +48,7 @@ struct AspeedSoCState {
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/*< public >*/
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ARMCPU cpu[ASPEED_CPUS_NUM];
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A15MPPrivState a7mpcore;
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ARMv7MState armv7m;
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MemoryRegion *dram_mr;
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MemoryRegion sram;
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AspeedVICState vic;
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@ -72,6 +74,7 @@ struct AspeedSoCState {
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AspeedSDHCIState emmc;
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AspeedLPCState lpc;
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uint32_t uart_default;
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Clock *sysclk;
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};
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#define TYPE_ASPEED_SOC "aspeed-soc"
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