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target/riscv/vector_helper: Fix build on 32-bit big endian hosts

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The code currently fails to compile on 32-bit big endian hosts:

 target/riscv/vector_helper.c: In function 'vext_clear':
 target/riscv/vector_helper.c:154:16: error: cast to pointer from integer
 of different size [-Werror=int-to-pointer-cast]
         memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1);
                ^
 target/riscv/vector_helper.c:155:16: error: cast to pointer from integer
 of different size [-Werror=int-to-pointer-cast]
         memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2);
                ^
 cc1: all warnings being treated as errors

We should not use "long long" (i.e. 64-bit) values here to avoid the
problem. Switch to our QEMU_ALIGN_PTR_DOWN/UP macros instead.

Fixes: 751538d5da ("add vector stride load and store instructions")
Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200804170055.2851-3-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Thomas Huth 2020-08-03 19:54:36 +02:00
parent 5896c53954
commit 35c7f5254b
1 changed files with 2 additions and 2 deletions
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4
target/riscv/vector_helper.c
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@ -151,8 +151,8 @@ static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
if (cnt % 8) {
part1 = 8 - (cnt % 8);
part2 = tot - cnt - part1;
memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1);
memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2);
memset(QEMU_ALIGN_PTR_DOWN(tail, 8), 0, part1);
memset(QEMU_ALIGN_PTR_UP(tail, 8), 0, part2);
} else {
memset(tail, 0, part2);
}