target/arm: Implement SVE Partition Break Group
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180613015641.5667-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
38cadeba0d
commit
35da316f5e
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@ -658,3 +658,21 @@ DEF_HELPER_FLAGS_5(sve_orn_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_nor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_nand_pppp, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_brkpa, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_brkpb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_brkpas, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_brkpbs, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_brka_z, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_brkb_z, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_brka_m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_brkb_m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_brkas_z, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_brkbs_z, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_brkas_m, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_brkbs_m, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_brkn, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_brkns, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32)
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@ -59,6 +59,7 @@
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&rri_esz rd rn imm esz
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&rrr_esz rd rn rm esz
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&rpr_esz rd pg rn esz
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&rpr_s rd pg rn s
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&rprr_s rd pg rn rm s
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&rprr_esz rd pg rn rm esz
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&rprrr_esz rd pg rn rm ra esz
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@ -78,6 +79,9 @@
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@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
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@rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
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# Two operand with governing predicate, flags setting
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@pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s
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# Three operand with unused vector element size
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@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
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@ -560,6 +564,21 @@ PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
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# SVE predicate next active
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PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
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### SVE Partition Break Group
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# SVE propagate break from previous partition
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BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s
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BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s
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# SVE partition break condition
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BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
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BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
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BRKA_m 00100101 0. 01000001 .... 0 .... 1 .... @pd_pg_pn_s
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BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s
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# SVE propagate break to next partition
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BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s
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### SVE Memory - 32-bit Gather and Unsized Contiguous Group
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# SVE load predicate register
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@ -2476,3 +2476,251 @@ DO_CMP_PPZI_D(sve_cmpls_ppzi_d, uint64_t, <=)
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#undef DO_CMP_PPZI_S
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#undef DO_CMP_PPZI_D
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#undef DO_CMP_PPZI
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/* Similar to the ARM LastActive pseudocode function. */
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static bool last_active_pred(void *vd, void *vg, intptr_t oprsz)
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{
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intptr_t i;
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for (i = QEMU_ALIGN_UP(oprsz, 8) - 8; i >= 0; i -= 8) {
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uint64_t pg = *(uint64_t *)(vg + i);
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if (pg) {
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return (pow2floor(pg) & *(uint64_t *)(vd + i)) != 0;
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}
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}
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return 0;
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}
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/* Compute a mask into RETB that is true for all G, up to and including
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* (if after) or excluding (if !after) the first G & N.
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* Return true if BRK found.
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*/
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static bool compute_brk(uint64_t *retb, uint64_t n, uint64_t g,
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bool brk, bool after)
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{
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uint64_t b;
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if (brk) {
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b = 0;
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} else if ((g & n) == 0) {
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/* For all G, no N are set; break not found. */
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b = g;
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} else {
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/* Break somewhere in N. Locate it. */
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b = g & n; /* guard true, pred true */
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b = b & -b; /* first such */
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if (after) {
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b = b | (b - 1); /* break after same */
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} else {
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b = b - 1; /* break before same */
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}
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brk = true;
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}
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*retb = b;
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return brk;
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}
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/* Compute a zeroing BRK. */
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static void compute_brk_z(uint64_t *d, uint64_t *n, uint64_t *g,
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intptr_t oprsz, bool after)
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{
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bool brk = false;
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intptr_t i;
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for (i = 0; i < DIV_ROUND_UP(oprsz, 8); ++i) {
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uint64_t this_b, this_g = g[i];
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brk = compute_brk(&this_b, n[i], this_g, brk, after);
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d[i] = this_b & this_g;
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}
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}
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/* Likewise, but also compute flags. */
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static uint32_t compute_brks_z(uint64_t *d, uint64_t *n, uint64_t *g,
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intptr_t oprsz, bool after)
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{
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uint32_t flags = PREDTEST_INIT;
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bool brk = false;
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intptr_t i;
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for (i = 0; i < DIV_ROUND_UP(oprsz, 8); ++i) {
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uint64_t this_b, this_d, this_g = g[i];
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brk = compute_brk(&this_b, n[i], this_g, brk, after);
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d[i] = this_d = this_b & this_g;
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flags = iter_predtest_fwd(this_d, this_g, flags);
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}
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return flags;
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}
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/* Compute a merging BRK. */
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static void compute_brk_m(uint64_t *d, uint64_t *n, uint64_t *g,
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intptr_t oprsz, bool after)
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{
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bool brk = false;
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intptr_t i;
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for (i = 0; i < DIV_ROUND_UP(oprsz, 8); ++i) {
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uint64_t this_b, this_g = g[i];
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brk = compute_brk(&this_b, n[i], this_g, brk, after);
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d[i] = (this_b & this_g) | (d[i] & ~this_g);
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}
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}
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/* Likewise, but also compute flags. */
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static uint32_t compute_brks_m(uint64_t *d, uint64_t *n, uint64_t *g,
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intptr_t oprsz, bool after)
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{
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uint32_t flags = PREDTEST_INIT;
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bool brk = false;
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intptr_t i;
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for (i = 0; i < oprsz / 8; ++i) {
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uint64_t this_b, this_d = d[i], this_g = g[i];
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brk = compute_brk(&this_b, n[i], this_g, brk, after);
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d[i] = this_d = (this_b & this_g) | (this_d & ~this_g);
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flags = iter_predtest_fwd(this_d, this_g, flags);
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}
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return flags;
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}
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static uint32_t do_zero(ARMPredicateReg *d, intptr_t oprsz)
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{
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/* It is quicker to zero the whole predicate than loop on OPRSZ.
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* The compiler should turn this into 4 64-bit integer stores.
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*/
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memset(d, 0, sizeof(ARMPredicateReg));
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return PREDTEST_INIT;
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}
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void HELPER(sve_brkpa)(void *vd, void *vn, void *vm, void *vg,
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uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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if (last_active_pred(vn, vg, oprsz)) {
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compute_brk_z(vd, vm, vg, oprsz, true);
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} else {
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do_zero(vd, oprsz);
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}
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}
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uint32_t HELPER(sve_brkpas)(void *vd, void *vn, void *vm, void *vg,
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uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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if (last_active_pred(vn, vg, oprsz)) {
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return compute_brks_z(vd, vm, vg, oprsz, true);
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} else {
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return do_zero(vd, oprsz);
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}
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}
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void HELPER(sve_brkpb)(void *vd, void *vn, void *vm, void *vg,
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uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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if (last_active_pred(vn, vg, oprsz)) {
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compute_brk_z(vd, vm, vg, oprsz, false);
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} else {
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do_zero(vd, oprsz);
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}
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}
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uint32_t HELPER(sve_brkpbs)(void *vd, void *vn, void *vm, void *vg,
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uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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if (last_active_pred(vn, vg, oprsz)) {
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return compute_brks_z(vd, vm, vg, oprsz, false);
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} else {
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return do_zero(vd, oprsz);
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}
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}
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void HELPER(sve_brka_z)(void *vd, void *vn, void *vg, uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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compute_brk_z(vd, vn, vg, oprsz, true);
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}
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uint32_t HELPER(sve_brkas_z)(void *vd, void *vn, void *vg, uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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return compute_brks_z(vd, vn, vg, oprsz, true);
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}
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void HELPER(sve_brkb_z)(void *vd, void *vn, void *vg, uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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compute_brk_z(vd, vn, vg, oprsz, false);
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}
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uint32_t HELPER(sve_brkbs_z)(void *vd, void *vn, void *vg, uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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return compute_brks_z(vd, vn, vg, oprsz, false);
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}
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void HELPER(sve_brka_m)(void *vd, void *vn, void *vg, uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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compute_brk_m(vd, vn, vg, oprsz, true);
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}
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uint32_t HELPER(sve_brkas_m)(void *vd, void *vn, void *vg, uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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return compute_brks_m(vd, vn, vg, oprsz, true);
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}
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void HELPER(sve_brkb_m)(void *vd, void *vn, void *vg, uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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compute_brk_m(vd, vn, vg, oprsz, false);
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}
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uint32_t HELPER(sve_brkbs_m)(void *vd, void *vn, void *vg, uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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return compute_brks_m(vd, vn, vg, oprsz, false);
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}
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void HELPER(sve_brkn)(void *vd, void *vn, void *vg, uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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if (!last_active_pred(vn, vg, oprsz)) {
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do_zero(vd, oprsz);
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}
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}
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/* As if PredTest(Ones(PL), D, esz). */
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static uint32_t predtest_ones(ARMPredicateReg *d, intptr_t oprsz,
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uint64_t esz_mask)
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{
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uint32_t flags = PREDTEST_INIT;
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intptr_t i;
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for (i = 0; i < oprsz / 8; i++) {
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flags = iter_predtest_fwd(d->p[i], esz_mask, flags);
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}
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if (oprsz & 7) {
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uint64_t mask = ~(-1ULL << (8 * (oprsz & 7)));
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flags = iter_predtest_fwd(d->p[i], esz_mask & mask, flags);
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}
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return flags;
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}
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uint32_t HELPER(sve_brkns)(void *vd, void *vn, void *vg, uint32_t pred_desc)
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{
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intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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if (last_active_pred(vn, vg, oprsz)) {
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return predtest_ones(vd, oprsz, -1);
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} else {
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return do_zero(vd, oprsz);
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}
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}
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@ -2853,6 +2853,112 @@ DO_PPZI(CMPLS, cmpls)
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#undef DO_PPZI
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/*
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*** SVE Partition Break Group
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*/
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static bool do_brk3(DisasContext *s, arg_rprr_s *a,
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gen_helper_gvec_4 *fn, gen_helper_gvec_flags_4 *fn_s)
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{
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if (!sve_access_check(s)) {
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return true;
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}
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unsigned vsz = pred_full_reg_size(s);
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/* Predicate sizes may be smaller and cannot use simd_desc. */
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TCGv_ptr d = tcg_temp_new_ptr();
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TCGv_ptr n = tcg_temp_new_ptr();
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TCGv_ptr m = tcg_temp_new_ptr();
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TCGv_ptr g = tcg_temp_new_ptr();
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TCGv_i32 t = tcg_const_i32(vsz - 2);
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tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
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tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
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tcg_gen_addi_ptr(m, cpu_env, pred_full_reg_offset(s, a->rm));
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tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
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if (a->s) {
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fn_s(t, d, n, m, g, t);
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do_pred_flags(t);
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} else {
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fn(d, n, m, g, t);
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}
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tcg_temp_free_ptr(d);
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tcg_temp_free_ptr(n);
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tcg_temp_free_ptr(m);
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tcg_temp_free_ptr(g);
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tcg_temp_free_i32(t);
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return true;
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}
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static bool do_brk2(DisasContext *s, arg_rpr_s *a,
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gen_helper_gvec_3 *fn, gen_helper_gvec_flags_3 *fn_s)
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{
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if (!sve_access_check(s)) {
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return true;
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}
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unsigned vsz = pred_full_reg_size(s);
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/* Predicate sizes may be smaller and cannot use simd_desc. */
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TCGv_ptr d = tcg_temp_new_ptr();
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TCGv_ptr n = tcg_temp_new_ptr();
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TCGv_ptr g = tcg_temp_new_ptr();
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TCGv_i32 t = tcg_const_i32(vsz - 2);
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tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
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tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
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tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
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if (a->s) {
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fn_s(t, d, n, g, t);
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do_pred_flags(t);
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} else {
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||||
fn(d, n, g, t);
|
||||
}
|
||||
tcg_temp_free_ptr(d);
|
||||
tcg_temp_free_ptr(n);
|
||||
tcg_temp_free_ptr(g);
|
||||
tcg_temp_free_i32(t);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_BRKPA(DisasContext *s, arg_rprr_s *a, uint32_t insn)
|
||||
{
|
||||
return do_brk3(s, a, gen_helper_sve_brkpa, gen_helper_sve_brkpas);
|
||||
}
|
||||
|
||||
static bool trans_BRKPB(DisasContext *s, arg_rprr_s *a, uint32_t insn)
|
||||
{
|
||||
return do_brk3(s, a, gen_helper_sve_brkpb, gen_helper_sve_brkpbs);
|
||||
}
|
||||
|
||||
static bool trans_BRKA_m(DisasContext *s, arg_rpr_s *a, uint32_t insn)
|
||||
{
|
||||
return do_brk2(s, a, gen_helper_sve_brka_m, gen_helper_sve_brkas_m);
|
||||
}
|
||||
|
||||
static bool trans_BRKB_m(DisasContext *s, arg_rpr_s *a, uint32_t insn)
|
||||
{
|
||||
return do_brk2(s, a, gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m);
|
||||
}
|
||||
|
||||
static bool trans_BRKA_z(DisasContext *s, arg_rpr_s *a, uint32_t insn)
|
||||
{
|
||||
return do_brk2(s, a, gen_helper_sve_brka_z, gen_helper_sve_brkas_z);
|
||||
}
|
||||
|
||||
static bool trans_BRKB_z(DisasContext *s, arg_rpr_s *a, uint32_t insn)
|
||||
{
|
||||
return do_brk2(s, a, gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z);
|
||||
}
|
||||
|
||||
static bool trans_BRKN(DisasContext *s, arg_rpr_s *a, uint32_t insn)
|
||||
{
|
||||
return do_brk2(s, a, gen_helper_sve_brkn, gen_helper_sve_brkns);
|
||||
}
|
||||
|
||||
/*
|
||||
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue