target/openrisc: Convert to CPUClass::tlb_fill
Cc: Stafford Horne <shorne@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -149,9 +149,8 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
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cc->set_pc = openrisc_cpu_set_pc;
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cc->gdb_read_register = openrisc_cpu_gdb_read_register;
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cc->gdb_write_register = openrisc_cpu_gdb_write_register;
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault;
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#else
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cc->tlb_fill = openrisc_cpu_tlb_fill;
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#ifndef CONFIG_USER_ONLY
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cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
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dc->vmsd = &vmstate_openrisc_cpu;
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#endif
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@ -344,8 +344,9 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void openrisc_translate_init(void);
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int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
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int rw, int mmu_idx);
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bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
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int print_insn_or1k(bfd_vma addr, disassemble_info *info);
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@ -107,16 +107,42 @@ static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address,
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cpu->env.lock_addr = -1;
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}
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int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
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int rw, int mmu_idx)
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bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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#ifdef CONFIG_USER_ONLY
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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raise_mmu_exception(cpu, address, EXCP_DPF);
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return 1;
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#else
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g_assert_not_reached();
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int excp = EXCP_DPF;
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#ifndef CONFIG_USER_ONLY
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int prot;
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hwaddr phys_addr;
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if (mmu_idx == MMU_NOMMU_IDX) {
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/* The mmu is disabled; lookups never fail. */
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get_phys_nommu(&phys_addr, &prot, addr);
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excp = 0;
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} else {
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bool super = mmu_idx == MMU_SUPERVISOR_IDX;
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int need = (access_type == MMU_INST_FETCH ? PAGE_EXEC
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: access_type == MMU_DATA_STORE ? PAGE_WRITE
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: PAGE_READ);
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excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super);
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}
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if (likely(excp == 0)) {
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tlb_set_page(cs, addr & TARGET_PAGE_MASK,
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phys_addr & TARGET_PAGE_MASK, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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if (probe) {
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return false;
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}
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#endif
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raise_mmu_exception(cpu, addr, excp);
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cpu_loop_exit_restore(cs, retaddr);
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}
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#ifndef CONFIG_USER_ONLY
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@ -156,29 +182,6 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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int prot, excp;
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hwaddr phys_addr;
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if (mmu_idx == MMU_NOMMU_IDX) {
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/* The mmu is disabled; lookups never fail. */
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get_phys_nommu(&phys_addr, &prot, addr);
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excp = 0;
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} else {
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bool super = mmu_idx == MMU_SUPERVISOR_IDX;
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int need = (access_type == MMU_INST_FETCH ? PAGE_EXEC
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: access_type == MMU_DATA_STORE ? PAGE_WRITE
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: PAGE_READ);
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excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super);
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}
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if (unlikely(excp)) {
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raise_mmu_exception(cpu, addr, excp);
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cpu_loop_exit_restore(cs, retaddr);
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}
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tlb_set_page(cs, addr & TARGET_PAGE_MASK,
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phys_addr & TARGET_PAGE_MASK, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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openrisc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, 0, retaddr);
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}
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#endif
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