target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -154,7 +154,7 @@ static void gen_lxvdsx(DisasContext *ctx)
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static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
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TCGv_i64 inh, TCGv_i64 inl)
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{
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TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF);
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TCGv_i64 mask = tcg_constant_i64(0x00FF00FF00FF00FF);
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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@ -825,7 +825,7 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
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REQUIRE_INSNS_FLAGS2(ctx, ISA300);
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REQUIRE_VSX(ctx);
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ro = tcg_const_i32(a->rc);
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ro = tcg_constant_i32(a->rc);
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xt = gen_avr_ptr(a->rt);
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xb = gen_avr_ptr(a->rb);
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@ -860,7 +860,7 @@ static void gen_##name(DisasContext *ctx) \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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opc = tcg_const_i32(ctx->opcode); \
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opc = tcg_constant_i32(ctx->opcode); \
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gen_helper_##name(cpu_env, opc); \
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}
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@ -900,7 +900,7 @@ static void gen_##name(DisasContext *ctx) \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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opc = tcg_const_i32(ctx->opcode); \
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opc = tcg_constant_i32(ctx->opcode); \
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xa = gen_vsr_ptr(xA(ctx->opcode)); \
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xb = gen_vsr_ptr(xB(ctx->opcode)); \
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gen_helper_##name(cpu_env, opc, xa, xb); \
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@ -915,7 +915,7 @@ static void gen_##name(DisasContext *ctx) \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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opc = tcg_const_i32(ctx->opcode); \
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opc = tcg_constant_i32(ctx->opcode); \
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xb = gen_vsr_ptr(xB(ctx->opcode)); \
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gen_helper_##name(cpu_env, opc, xb); \
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}
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@ -929,7 +929,7 @@ static void gen_##name(DisasContext *ctx) \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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opc = tcg_const_i32(ctx->opcode); \
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opc = tcg_constant_i32(ctx->opcode); \
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xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
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xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
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xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
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@ -945,7 +945,7 @@ static void gen_##name(DisasContext *ctx) \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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opc = tcg_const_i32(ctx->opcode); \
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opc = tcg_constant_i32(ctx->opcode); \
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xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
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xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
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gen_helper_##name(cpu_env, opc, xt, xb); \
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@ -960,7 +960,7 @@ static void gen_##name(DisasContext *ctx) \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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opc = tcg_const_i32(ctx->opcode); \
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opc = tcg_constant_i32(ctx->opcode); \
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xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
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xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
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gen_helper_##name(cpu_env, opc, xa, xb); \
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@ -1994,8 +1994,8 @@ static void gen_xsxsigdp(DisasContext *ctx)
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exp = tcg_temp_new_i64();
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t0 = tcg_temp_new_i64();
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t1 = tcg_temp_new_i64();
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zr = tcg_const_i64(0);
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nan = tcg_const_i64(2047);
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zr = tcg_constant_i64(0);
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nan = tcg_constant_i64(2047);
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get_cpu_vsr(t1, xB(ctx->opcode), true);
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tcg_gen_extract_i64(exp, t1, 52, 11);
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@ -2026,8 +2026,8 @@ static void gen_xsxsigqp(DisasContext *ctx)
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get_cpu_vsr(xbl, rB(ctx->opcode) + 32, false);
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exp = tcg_temp_new_i64();
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t0 = tcg_temp_new_i64();
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zr = tcg_const_i64(0);
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nan = tcg_const_i64(32767);
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zr = tcg_constant_i64(0);
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nan = tcg_constant_i64(32767);
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tcg_gen_extract_i64(exp, xbh, 48, 15);
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tcg_gen_movi_i64(t0, 0x0001000000000000);
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@ -2193,8 +2193,8 @@ static void gen_xvxsigdp(DisasContext *ctx)
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get_cpu_vsr(xbl, xB(ctx->opcode), false);
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exp = tcg_temp_new_i64();
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t0 = tcg_temp_new_i64();
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zr = tcg_const_i64(0);
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nan = tcg_const_i64(2047);
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zr = tcg_constant_i64(0);
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nan = tcg_constant_i64(2047);
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tcg_gen_extract_i64(exp, xbh, 52, 11);
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tcg_gen_movi_i64(t0, 0x0010000000000000);
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