tcg: Introduce negsetcond opcodes
Introduce a new opcode for negative setcond. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
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13d885b0ad
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3635502dd0
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@ -498,6 +498,12 @@ Conditional moves
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| Set *dest* to 1 if (*t1* *cond* *t2*) is true, otherwise set to 0.
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* - negsetcond_i32/i64 *dest*, *t1*, *t2*, *cond*
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- | *dest* = -(*t1* *cond* *t2*)
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| Set *dest* to -1 if (*t1* *cond* *t2*) is true, otherwise set to 0.
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* - movcond_i32/i64 *dest*, *c1*, *c2*, *v1*, *v2*, *cond*
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- | *dest* = (*c1* *cond* *c2* ? *v1* : *v2*)
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@ -344,6 +344,8 @@ void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
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TCGv_i32 arg1, TCGv_i32 arg2);
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void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
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TCGv_i32 arg1, int32_t arg2);
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void tcg_gen_negsetcond_i32(TCGCond cond, TCGv_i32 ret,
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TCGv_i32 arg1, TCGv_i32 arg2);
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void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
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TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
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void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
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@ -540,6 +542,8 @@ void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
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TCGv_i64 arg1, TCGv_i64 arg2);
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void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
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TCGv_i64 arg1, int64_t arg2);
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void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 ret,
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TCGv_i64 arg1, TCGv_i64 arg2);
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void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
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TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
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void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
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@ -200,6 +200,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
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#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
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#define tcg_gen_setcond_tl tcg_gen_setcond_i64
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#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
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#define tcg_gen_negsetcond_tl tcg_gen_negsetcond_i64
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#define tcg_gen_mul_tl tcg_gen_mul_i64
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#define tcg_gen_muli_tl tcg_gen_muli_i64
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#define tcg_gen_div_tl tcg_gen_div_i64
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@ -317,6 +318,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
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#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
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#define tcg_gen_setcond_tl tcg_gen_setcond_i32
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#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
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#define tcg_gen_negsetcond_tl tcg_gen_negsetcond_i32
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#define tcg_gen_mul_tl tcg_gen_mul_i32
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#define tcg_gen_muli_tl tcg_gen_muli_i32
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#define tcg_gen_div_tl tcg_gen_div_i32
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@ -46,6 +46,7 @@ DEF(mb, 0, 0, 1, 0)
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DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
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DEF(setcond_i32, 1, 2, 1, 0)
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DEF(negsetcond_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_negsetcond_i32))
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DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
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/* load/store */
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DEF(ld8u_i32, 1, 1, 1, 0)
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@ -111,6 +112,7 @@ DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32))
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DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
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DEF(setcond_i64, 1, 2, 1, IMPL64)
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DEF(negsetcond_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_negsetcond_i64))
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DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
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/* load/store */
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DEF(ld8u_i64, 1, 1, 1, IMPL64)
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@ -97,6 +97,7 @@ typedef uint64_t TCGRegSet;
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_movcond_i64 0
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#define TCG_TARGET_HAS_negsetcond_i64 0
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#define TCG_TARGET_HAS_add2_i64 0
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#define TCG_TARGET_HAS_sub2_i64 0
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#define TCG_TARGET_HAS_mulu2_i64 0
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@ -86,6 +86,7 @@ typedef enum {
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 0
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 0
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@ -122,6 +123,7 @@ typedef enum {
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#define TCG_TARGET_HAS_sextract_i64 1
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#define TCG_TARGET_HAS_extract2_i64 1
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_negsetcond_i64 0
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 0
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@ -116,6 +116,7 @@ extern bool use_neon_instructions;
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#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_extract2_i32 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 1
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#define TCG_TARGET_HAS_muls2_i32 1
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#define TCG_TARGET_HAS_muluh_i32 0
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@ -150,6 +150,7 @@ typedef enum {
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 0
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 1
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@ -186,6 +187,7 @@ typedef enum {
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_extract2_i64 1
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_negsetcond_i64 0
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 1
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@ -86,6 +86,7 @@ typedef enum {
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/* optional instructions */
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 0
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_rem_i32 1
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#define TCG_TARGET_HAS_div2_i32 0
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@ -122,6 +123,7 @@ typedef enum {
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/* 64-bit operations */
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_negsetcond_i64 0
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rem_i64 1
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#define TCG_TARGET_HAS_div2_i64 0
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@ -156,6 +158,7 @@ typedef enum {
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#define TCG_TARGET_HAS_muls2_i64 0
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#define TCG_TARGET_HAS_muluh_i64 1
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#define TCG_TARGET_HAS_mulsh_i64 1
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#define TCG_TARGET_HAS_qemu_ldst_i128 0
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#define TCG_TARGET_DEFAULT_MO (0)
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@ -128,6 +128,7 @@ extern bool use_mips32r2_instructions;
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#define TCG_TARGET_HAS_muluh_i32 1
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#define TCG_TARGET_HAS_mulsh_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 0
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_add2_i32 0
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@ -149,6 +150,7 @@ extern bool use_mips32r2_instructions;
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#define TCG_TARGET_HAS_mulsh_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext32u_i64 1
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#define TCG_TARGET_HAS_negsetcond_i64 0
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#endif
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/* optional instructions detected at runtime */
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@ -1567,14 +1567,22 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
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if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
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uint64_t tv = arg_info(op->args[3])->val;
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uint64_t fv = arg_info(op->args[4])->val;
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TCGOpcode opc;
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TCGOpcode opc, negopc = 0;
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switch (ctx->type) {
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case TCG_TYPE_I32:
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opc = INDEX_op_setcond_i32;
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if (TCG_TARGET_HAS_negsetcond_i32) {
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negopc = INDEX_op_negsetcond_i32;
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}
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tv = (int32_t)tv;
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fv = (int32_t)fv;
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break;
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case TCG_TYPE_I64:
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opc = INDEX_op_setcond_i64;
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if (TCG_TARGET_HAS_negsetcond_i64) {
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negopc = INDEX_op_negsetcond_i64;
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}
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break;
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default:
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g_assert_not_reached();
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@ -1586,6 +1594,14 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
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} else if (fv == 1 && tv == 0) {
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op->opc = opc;
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op->args[3] = tcg_invert_cond(cond);
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} else if (negopc) {
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if (tv == -1 && fv == 0) {
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op->opc = negopc;
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op->args[3] = cond;
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} else if (fv == -1 && tv == 0) {
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op->opc = negopc;
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op->args[3] = tcg_invert_cond(cond);
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}
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}
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}
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return false;
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@ -1796,6 +1812,26 @@ static bool fold_setcond(OptContext *ctx, TCGOp *op)
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return false;
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}
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static bool fold_negsetcond(OptContext *ctx, TCGOp *op)
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{
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TCGCond cond = op->args[3];
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int i;
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if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) {
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op->args[3] = cond = tcg_swap_cond(cond);
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}
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i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond);
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if (i >= 0) {
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return tcg_opt_gen_movi(ctx, op, op->args[0], -i);
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}
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/* Value is {0,-1} so all bits are repetitions of the sign. */
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ctx->s_mask = -1;
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return false;
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}
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static bool fold_setcond2(OptContext *ctx, TCGOp *op)
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{
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TCGCond cond = op->args[5];
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@ -2253,6 +2289,9 @@ void tcg_optimize(TCGContext *s)
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CASE_OP_32_64(setcond):
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done = fold_setcond(&ctx, op);
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break;
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CASE_OP_32_64(negsetcond):
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done = fold_negsetcond(&ctx, op);
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break;
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case INDEX_op_setcond2_i32:
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done = fold_setcond2(&ctx, op);
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break;
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@ -97,6 +97,7 @@ typedef enum {
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#define TCG_TARGET_HAS_sextract_i32 0
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 0
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#define TCG_TARGET_HAS_muls2_i32 0
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#define TCG_TARGET_HAS_muluh_i32 1
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_negsetcond_i64 0
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 0
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@ -88,6 +88,7 @@ extern bool have_zbb;
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/* optional instructions */
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 0
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_rem_i32 1
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#define TCG_TARGET_HAS_div2_i32 0
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#define TCG_TARGET_HAS_qemu_st8_i32 0
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_negsetcond_i64 0
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rem_i64 1
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#define TCG_TARGET_HAS_div2_i64 0
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@ -96,6 +96,7 @@ extern uint64_t s390_facilities[3];
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#define TCG_TARGET_HAS_sextract_i32 0
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 0
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 0
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_negsetcond_i64 0
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 1
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#define TCG_TARGET_HAS_sextract_i32 0
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 0
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 1
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_negsetcond_i64 0
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 0
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36
tcg/tcg-op.c
36
tcg/tcg-op.c
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@ -276,6 +276,21 @@ void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
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tcg_gen_setcond_i32(cond, ret, arg1, tcg_constant_i32(arg2));
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}
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void tcg_gen_negsetcond_i32(TCGCond cond, TCGv_i32 ret,
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TCGv_i32 arg1, TCGv_i32 arg2)
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{
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if (cond == TCG_COND_ALWAYS) {
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tcg_gen_movi_i32(ret, -1);
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} else if (cond == TCG_COND_NEVER) {
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tcg_gen_movi_i32(ret, 0);
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} else if (TCG_TARGET_HAS_negsetcond_i32) {
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tcg_gen_op4i_i32(INDEX_op_negsetcond_i32, ret, arg1, arg2, cond);
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} else {
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tcg_gen_setcond_i32(cond, ret, arg1, arg2);
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tcg_gen_neg_i32(ret, ret);
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}
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}
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void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
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{
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if (arg2 == 0) {
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@ -1567,6 +1582,27 @@ void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
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}
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}
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void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 ret,
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TCGv_i64 arg1, TCGv_i64 arg2)
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{
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if (cond == TCG_COND_ALWAYS) {
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tcg_gen_movi_i64(ret, -1);
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} else if (cond == TCG_COND_NEVER) {
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tcg_gen_movi_i64(ret, 0);
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} else if (TCG_TARGET_HAS_negsetcond_i64) {
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tcg_gen_op4i_i64(INDEX_op_negsetcond_i64, ret, arg1, arg2, cond);
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} else if (TCG_TARGET_REG_BITS == 32) {
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tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
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TCGV_LOW(arg1), TCGV_HIGH(arg1),
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TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
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tcg_gen_neg_i32(TCGV_LOW(ret), TCGV_LOW(ret));
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tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_LOW(ret));
|
||||
} else {
|
||||
tcg_gen_setcond_i64(cond, ret, arg1, arg2);
|
||||
tcg_gen_neg_i64(ret, ret);
|
||||
}
|
||||
}
|
||||
|
||||
void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
|
||||
{
|
||||
if (arg2 == 0) {
|
||||
|
|
|
@ -1879,6 +1879,8 @@ bool tcg_op_supported(TCGOpcode op)
|
|||
case INDEX_op_sar_i32:
|
||||
return true;
|
||||
|
||||
case INDEX_op_negsetcond_i32:
|
||||
return TCG_TARGET_HAS_negsetcond_i32;
|
||||
case INDEX_op_movcond_i32:
|
||||
return TCG_TARGET_HAS_movcond_i32;
|
||||
case INDEX_op_div_i32:
|
||||
|
@ -1977,6 +1979,8 @@ bool tcg_op_supported(TCGOpcode op)
|
|||
case INDEX_op_extu_i32_i64:
|
||||
return TCG_TARGET_REG_BITS == 64;
|
||||
|
||||
case INDEX_op_negsetcond_i64:
|
||||
return TCG_TARGET_HAS_negsetcond_i64;
|
||||
case INDEX_op_movcond_i64:
|
||||
return TCG_TARGET_HAS_movcond_i64;
|
||||
case INDEX_op_div_i64:
|
||||
|
@ -2509,11 +2513,13 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
|
|||
switch (c) {
|
||||
case INDEX_op_brcond_i32:
|
||||
case INDEX_op_setcond_i32:
|
||||
case INDEX_op_negsetcond_i32:
|
||||
case INDEX_op_movcond_i32:
|
||||
case INDEX_op_brcond2_i32:
|
||||
case INDEX_op_setcond2_i32:
|
||||
case INDEX_op_brcond_i64:
|
||||
case INDEX_op_setcond_i64:
|
||||
case INDEX_op_negsetcond_i64:
|
||||
case INDEX_op_movcond_i64:
|
||||
case INDEX_op_cmp_vec:
|
||||
case INDEX_op_cmpsel_vec:
|
||||
|
|
|
@ -70,6 +70,7 @@
|
|||
#define TCG_TARGET_HAS_orc_i32 1
|
||||
#define TCG_TARGET_HAS_rot_i32 1
|
||||
#define TCG_TARGET_HAS_movcond_i32 1
|
||||
#define TCG_TARGET_HAS_negsetcond_i32 0
|
||||
#define TCG_TARGET_HAS_muls2_i32 1
|
||||
#define TCG_TARGET_HAS_muluh_i32 0
|
||||
#define TCG_TARGET_HAS_mulsh_i32 0
|
||||
|
@ -104,6 +105,7 @@
|
|||
#define TCG_TARGET_HAS_orc_i64 1
|
||||
#define TCG_TARGET_HAS_rot_i64 1
|
||||
#define TCG_TARGET_HAS_movcond_i64 1
|
||||
#define TCG_TARGET_HAS_negsetcond_i64 0
|
||||
#define TCG_TARGET_HAS_muls2_i64 1
|
||||
#define TCG_TARGET_HAS_add2_i32 1
|
||||
#define TCG_TARGET_HAS_sub2_i32 1
|
||||
|
|
Loading…
Reference in New Issue