hw/misc: Add a model of the Xilinx Versal CRL
Add a model of the Xilinx Versal CRL. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Frederic Konrad <fkonrad@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Edgar E. Iglesias
Peter Maydell
parent
67a645a351
commit
369e5cb0c9
@ -86,6 +86,7 @@ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
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softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
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specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
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specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
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specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
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softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
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'xlnx-versal-xramc.c',
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'xlnx-versal-pmc-iou-slcr.c',
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421
hw/misc/xlnx-versal-crl.c
Normal file
421
hw/misc/xlnx-versal-crl.c
Normal file
@ -0,0 +1,421 @@
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/*
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* QEMU model of the Clock-Reset-LPD (CRL).
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*
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* Copyright (c) 2022 Advanced Micro Devices, Inc.
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Written by Edgar E. Iglesias <edgar.iglesias@amd.com>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/bitops.h"
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#include "migration/vmstate.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/register.h"
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#include "hw/resettable.h"
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#include "target/arm/arm-powerctl.h"
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#include "hw/misc/xlnx-versal-crl.h"
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#ifndef XLNX_VERSAL_CRL_ERR_DEBUG
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#define XLNX_VERSAL_CRL_ERR_DEBUG 0
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#endif
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static void crl_update_irq(XlnxVersalCRL *s)
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{
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bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
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qemu_set_irq(s->irq, pending);
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}
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static void crl_status_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
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crl_update_irq(s);
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}
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static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
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uint32_t val = val64;
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s->regs[R_IR_MASK] &= ~val;
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crl_update_irq(s);
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return 0;
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}
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static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
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uint32_t val = val64;
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s->regs[R_IR_MASK] |= val;
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crl_update_irq(s);
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return 0;
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}
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static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev,
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bool rst_old, bool rst_new)
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{
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device_cold_reset(dev);
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}
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static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu,
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bool rst_old, bool rst_new)
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{
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if (rst_new) {
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arm_set_cpu_off(armcpu->mp_affinity);
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} else {
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arm_set_cpu_on_and_reset(armcpu->mp_affinity);
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}
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}
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#define REGFIELD_RESET(type, s, reg, f, new_val, dev) { \
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bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f); \
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bool new_f = FIELD_EX32(new_val, reg, f); \
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\
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/* Detect edges. */ \
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if (dev && old_f != new_f) { \
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crl_reset_ ## type(s, dev, old_f, new_f); \
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} \
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}
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static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
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REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]);
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REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]);
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return val64;
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}
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static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
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int i;
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/* A single register fans out to all ADMA reset inputs. */
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for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) {
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REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]);
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}
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return val64;
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}
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static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
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REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]);
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return val64;
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}
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static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
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REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]);
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return val64;
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}
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static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
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REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]);
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return val64;
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}
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static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
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REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]);
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return val64;
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}
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static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
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REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb);
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return val64;
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}
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static const RegisterAccessInfo crl_regs_info[] = {
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{ .name = "ERR_CTRL", .addr = A_ERR_CTRL,
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},{ .name = "IR_STATUS", .addr = A_IR_STATUS,
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.w1c = 0x1,
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.post_write = crl_status_postw,
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},{ .name = "IR_MASK", .addr = A_IR_MASK,
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.reset = 0x1,
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.ro = 0x1,
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},{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
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.pre_write = crl_enable_prew,
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},{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
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.pre_write = crl_disable_prew,
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},{ .name = "WPROT", .addr = A_WPROT,
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},{ .name = "PLL_CLK_OTHER_DMN", .addr = A_PLL_CLK_OTHER_DMN,
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.reset = 0x1,
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.rsvd = 0xe,
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},{ .name = "RPLL_CTRL", .addr = A_RPLL_CTRL,
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.reset = 0x24809,
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.rsvd = 0xf88c00f6,
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},{ .name = "RPLL_CFG", .addr = A_RPLL_CFG,
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.reset = 0x2000000,
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.rsvd = 0x1801210,
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},{ .name = "RPLL_FRAC_CFG", .addr = A_RPLL_FRAC_CFG,
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.rsvd = 0x7e330000,
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},{ .name = "PLL_STATUS", .addr = A_PLL_STATUS,
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.reset = R_PLL_STATUS_RPLL_STABLE_MASK |
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R_PLL_STATUS_RPLL_LOCK_MASK,
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.rsvd = 0xfa,
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.ro = 0x5,
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},{ .name = "RPLL_TO_XPD_CTRL", .addr = A_RPLL_TO_XPD_CTRL,
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.reset = 0x2000100,
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.rsvd = 0xfdfc00ff,
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},{ .name = "LPD_TOP_SWITCH_CTRL", .addr = A_LPD_TOP_SWITCH_CTRL,
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.reset = 0x6000300,
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.rsvd = 0xf9fc00f8,
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},{ .name = "LPD_LSBUS_CTRL", .addr = A_LPD_LSBUS_CTRL,
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.reset = 0x2000800,
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.rsvd = 0xfdfc00f8,
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},{ .name = "CPU_R5_CTRL", .addr = A_CPU_R5_CTRL,
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.reset = 0xe000300,
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.rsvd = 0xe1fc00f8,
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},{ .name = "IOU_SWITCH_CTRL", .addr = A_IOU_SWITCH_CTRL,
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.reset = 0x2000500,
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.rsvd = 0xfdfc00f8,
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},{ .name = "GEM0_REF_CTRL", .addr = A_GEM0_REF_CTRL,
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.reset = 0xe000a00,
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.rsvd = 0xf1fc00f8,
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},{ .name = "GEM1_REF_CTRL", .addr = A_GEM1_REF_CTRL,
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.reset = 0xe000a00,
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.rsvd = 0xf1fc00f8,
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},{ .name = "GEM_TSU_REF_CTRL", .addr = A_GEM_TSU_REF_CTRL,
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.reset = 0x300,
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.rsvd = 0xfdfc00f8,
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},{ .name = "USB0_BUS_REF_CTRL", .addr = A_USB0_BUS_REF_CTRL,
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.reset = 0x2001900,
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.rsvd = 0xfdfc00f8,
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},{ .name = "UART0_REF_CTRL", .addr = A_UART0_REF_CTRL,
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.reset = 0xc00,
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.rsvd = 0xfdfc00f8,
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},{ .name = "UART1_REF_CTRL", .addr = A_UART1_REF_CTRL,
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.reset = 0xc00,
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.rsvd = 0xfdfc00f8,
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},{ .name = "SPI0_REF_CTRL", .addr = A_SPI0_REF_CTRL,
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.reset = 0x600,
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.rsvd = 0xfdfc00f8,
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},{ .name = "SPI1_REF_CTRL", .addr = A_SPI1_REF_CTRL,
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.reset = 0x600,
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.rsvd = 0xfdfc00f8,
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},{ .name = "CAN0_REF_CTRL", .addr = A_CAN0_REF_CTRL,
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.reset = 0xc00,
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.rsvd = 0xfdfc00f8,
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},{ .name = "CAN1_REF_CTRL", .addr = A_CAN1_REF_CTRL,
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.reset = 0xc00,
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.rsvd = 0xfdfc00f8,
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},{ .name = "I2C0_REF_CTRL", .addr = A_I2C0_REF_CTRL,
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.reset = 0xc00,
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.rsvd = 0xfdfc00f8,
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},{ .name = "I2C1_REF_CTRL", .addr = A_I2C1_REF_CTRL,
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.reset = 0xc00,
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.rsvd = 0xfdfc00f8,
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},{ .name = "DBG_LPD_CTRL", .addr = A_DBG_LPD_CTRL,
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.reset = 0x300,
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.rsvd = 0xfdfc00f8,
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},{ .name = "TIMESTAMP_REF_CTRL", .addr = A_TIMESTAMP_REF_CTRL,
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.reset = 0x2000c00,
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.rsvd = 0xfdfc00f8,
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},{ .name = "CRL_SAFETY_CHK", .addr = A_CRL_SAFETY_CHK,
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},{ .name = "PSM_REF_CTRL", .addr = A_PSM_REF_CTRL,
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.reset = 0xf04,
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.rsvd = 0xfffc00f8,
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},{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL,
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.reset = 0x300,
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.rsvd = 0xfdfc00f8,
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},{ .name = "CPM_TOPSW_REF_CTRL", .addr = A_CPM_TOPSW_REF_CTRL,
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.reset = 0x300,
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.rsvd = 0xfdfc00f8,
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},{ .name = "USB3_DUAL_REF_CTRL", .addr = A_USB3_DUAL_REF_CTRL,
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.reset = 0x3c00,
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.rsvd = 0xfdfc00f8,
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},{ .name = "RST_CPU_R5", .addr = A_RST_CPU_R5,
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.reset = 0x17,
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.rsvd = 0x8,
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.pre_write = crl_rst_r5_prew,
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},{ .name = "RST_ADMA", .addr = A_RST_ADMA,
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.reset = 0x1,
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.pre_write = crl_rst_adma_prew,
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},{ .name = "RST_GEM0", .addr = A_RST_GEM0,
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.reset = 0x1,
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.pre_write = crl_rst_gem0_prew,
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},{ .name = "RST_GEM1", .addr = A_RST_GEM1,
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.reset = 0x1,
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.pre_write = crl_rst_gem1_prew,
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},{ .name = "RST_SPARE", .addr = A_RST_SPARE,
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.reset = 0x1,
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},{ .name = "RST_USB0", .addr = A_RST_USB0,
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.reset = 0x1,
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.pre_write = crl_rst_usb_prew,
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},{ .name = "RST_UART0", .addr = A_RST_UART0,
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.reset = 0x1,
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.pre_write = crl_rst_uart0_prew,
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},{ .name = "RST_UART1", .addr = A_RST_UART1,
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.reset = 0x1,
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.pre_write = crl_rst_uart1_prew,
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},{ .name = "RST_SPI0", .addr = A_RST_SPI0,
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.reset = 0x1,
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},{ .name = "RST_SPI1", .addr = A_RST_SPI1,
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.reset = 0x1,
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},{ .name = "RST_CAN0", .addr = A_RST_CAN0,
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.reset = 0x1,
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},{ .name = "RST_CAN1", .addr = A_RST_CAN1,
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.reset = 0x1,
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},{ .name = "RST_I2C0", .addr = A_RST_I2C0,
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.reset = 0x1,
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},{ .name = "RST_I2C1", .addr = A_RST_I2C1,
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.reset = 0x1,
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},{ .name = "RST_DBG_LPD", .addr = A_RST_DBG_LPD,
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.reset = 0x33,
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.rsvd = 0xcc,
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},{ .name = "RST_GPIO", .addr = A_RST_GPIO,
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.reset = 0x1,
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},{ .name = "RST_TTC", .addr = A_RST_TTC,
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.reset = 0xf,
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},{ .name = "RST_TIMESTAMP", .addr = A_RST_TIMESTAMP,
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.reset = 0x1,
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},{ .name = "RST_SWDT", .addr = A_RST_SWDT,
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.reset = 0x1,
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},{ .name = "RST_OCM", .addr = A_RST_OCM,
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},{ .name = "RST_IPI", .addr = A_RST_IPI,
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},{ .name = "RST_FPD", .addr = A_RST_FPD,
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.reset = 0x3,
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},{ .name = "PSM_RST_MODE", .addr = A_PSM_RST_MODE,
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.reset = 0x1,
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.rsvd = 0xf8,
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}
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};
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static void crl_reset_enter(Object *obj, ResetType type)
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{
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
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register_reset(&s->regs_info[i]);
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}
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}
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static void crl_reset_hold(Object *obj)
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{
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
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crl_update_irq(s);
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}
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static const MemoryRegionOps crl_ops = {
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.read = register_read_memory,
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.write = register_write_memory,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void crl_init(Object *obj)
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{
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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int i;
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s->reg_array =
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register_init_block32(DEVICE(obj), crl_regs_info,
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ARRAY_SIZE(crl_regs_info),
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s->regs_info, s->regs,
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&crl_ops,
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XLNX_VERSAL_CRL_ERR_DEBUG,
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CRL_R_MAX * 4);
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sysbus_init_mmio(sbd, &s->reg_array->mem);
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sysbus_init_irq(sbd, &s->irq);
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for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) {
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object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU,
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(Object **)&s->cfg.cpu_r5[i],
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qdev_prop_allow_set_link_before_realize,
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OBJ_PROP_LINK_STRONG);
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}
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for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) {
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object_property_add_link(obj, "adma[*]", TYPE_DEVICE,
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(Object **)&s->cfg.adma[i],
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qdev_prop_allow_set_link_before_realize,
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OBJ_PROP_LINK_STRONG);
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}
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for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) {
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object_property_add_link(obj, "uart[*]", TYPE_DEVICE,
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(Object **)&s->cfg.uart[i],
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qdev_prop_allow_set_link_before_realize,
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OBJ_PROP_LINK_STRONG);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) {
|
||||
object_property_add_link(obj, "gem[*]", TYPE_DEVICE,
|
||||
(Object **)&s->cfg.gem[i],
|
||||
qdev_prop_allow_set_link_before_realize,
|
||||
OBJ_PROP_LINK_STRONG);
|
||||
}
|
||||
|
||||
object_property_add_link(obj, "usb", TYPE_DEVICE,
|
||||
(Object **)&s->cfg.gem[i],
|
||||
qdev_prop_allow_set_link_before_realize,
|
||||
OBJ_PROP_LINK_STRONG);
|
||||
}
|
||||
|
||||
static void crl_finalize(Object *obj)
|
||||
{
|
||||
XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
|
||||
register_finalize_block(s->reg_array);
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_crl = {
|
||||
.name = TYPE_XLNX_VERSAL_CRL,
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX),
|
||||
VMSTATE_END_OF_LIST(),
|
||||
}
|
||||
};
|
||||
|
||||
static void crl_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
ResettableClass *rc = RESETTABLE_CLASS(klass);
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->vmsd = &vmstate_crl;
|
||||
|
||||
rc->phases.enter = crl_reset_enter;
|
||||
rc->phases.hold = crl_reset_hold;
|
||||
}
|
||||
|
||||
static const TypeInfo crl_info = {
|
||||
.name = TYPE_XLNX_VERSAL_CRL,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(XlnxVersalCRL),
|
||||
.class_init = crl_class_init,
|
||||
.instance_init = crl_init,
|
||||
.instance_finalize = crl_finalize,
|
||||
};
|
||||
|
||||
static void crl_register_types(void)
|
||||
{
|
||||
type_register_static(&crl_info);
|
||||
}
|
||||
|
||||
type_init(crl_register_types)
|
||||
235
include/hw/misc/xlnx-versal-crl.h
Normal file
235
include/hw/misc/xlnx-versal-crl.h
Normal file
@ -0,0 +1,235 @@
|
||||
/*
|
||||
* QEMU model of the Clock-Reset-LPD (CRL).
|
||||
*
|
||||
* Copyright (c) 2022 Xilinx Inc.
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*
|
||||
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
|
||||
*/
|
||||
#ifndef HW_MISC_XLNX_VERSAL_CRL_H
|
||||
#define HW_MISC_XLNX_VERSAL_CRL_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/register.h"
|
||||
#include "target/arm/cpu.h"
|
||||
|
||||
#define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)
|
||||
|
||||
REG32(ERR_CTRL, 0x0)
|
||||
FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
|
||||
REG32(IR_STATUS, 0x4)
|
||||
FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
|
||||
REG32(IR_MASK, 0x8)
|
||||
FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
|
||||
REG32(IR_ENABLE, 0xc)
|
||||
FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
|
||||
REG32(IR_DISABLE, 0x10)
|
||||
FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
|
||||
REG32(WPROT, 0x1c)
|
||||
FIELD(WPROT, ACTIVE, 0, 1)
|
||||
REG32(PLL_CLK_OTHER_DMN, 0x20)
|
||||
FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1)
|
||||
REG32(RPLL_CTRL, 0x40)
|
||||
FIELD(RPLL_CTRL, POST_SRC, 24, 3)
|
||||
FIELD(RPLL_CTRL, PRE_SRC, 20, 3)
|
||||
FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2)
|
||||
FIELD(RPLL_CTRL, FBDIV, 8, 8)
|
||||
FIELD(RPLL_CTRL, BYPASS, 3, 1)
|
||||
FIELD(RPLL_CTRL, RESET, 0, 1)
|
||||
REG32(RPLL_CFG, 0x44)
|
||||
FIELD(RPLL_CFG, LOCK_DLY, 25, 7)
|
||||
FIELD(RPLL_CFG, LOCK_CNT, 13, 10)
|
||||
FIELD(RPLL_CFG, LFHF, 10, 2)
|
||||
FIELD(RPLL_CFG, CP, 5, 4)
|
||||
FIELD(RPLL_CFG, RES, 0, 4)
|
||||
REG32(RPLL_FRAC_CFG, 0x48)
|
||||
FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1)
|
||||
FIELD(RPLL_FRAC_CFG, SEED, 22, 3)
|
||||
FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1)
|
||||
FIELD(RPLL_FRAC_CFG, ORDER, 18, 1)
|
||||
FIELD(RPLL_FRAC_CFG, DATA, 0, 16)
|
||||
REG32(PLL_STATUS, 0x50)
|
||||
FIELD(PLL_STATUS, RPLL_STABLE, 2, 1)
|
||||
FIELD(PLL_STATUS, RPLL_LOCK, 0, 1)
|
||||
REG32(RPLL_TO_XPD_CTRL, 0x100)
|
||||
FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1)
|
||||
FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
|
||||
REG32(LPD_TOP_SWITCH_CTRL, 0x104)
|
||||
FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1)
|
||||
FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1)
|
||||
FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3)
|
||||
REG32(LPD_LSBUS_CTRL, 0x108)
|
||||
FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1)
|
||||
FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3)
|
||||
REG32(CPU_R5_CTRL, 0x10c)
|
||||
FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1)
|
||||
FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1)
|
||||
FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1)
|
||||
FIELD(CPU_R5_CTRL, CLKACT, 25, 1)
|
||||
FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(CPU_R5_CTRL, SRCSEL, 0, 3)
|
||||
REG32(IOU_SWITCH_CTRL, 0x114)
|
||||
FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1)
|
||||
FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3)
|
||||
REG32(GEM0_REF_CTRL, 0x118)
|
||||
FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1)
|
||||
FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1)
|
||||
FIELD(GEM0_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(GEM1_REF_CTRL, 0x11c)
|
||||
FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1)
|
||||
FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1)
|
||||
FIELD(GEM1_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(GEM_TSU_REF_CTRL, 0x120)
|
||||
FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(USB0_BUS_REF_CTRL, 0x124)
|
||||
FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(UART0_REF_CTRL, 0x128)
|
||||
FIELD(UART0_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(UART0_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(UART1_REF_CTRL, 0x12c)
|
||||
FIELD(UART1_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(UART1_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(SPI0_REF_CTRL, 0x130)
|
||||
FIELD(SPI0_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(SPI1_REF_CTRL, 0x134)
|
||||
FIELD(SPI1_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(CAN0_REF_CTRL, 0x138)
|
||||
FIELD(CAN0_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(CAN1_REF_CTRL, 0x13c)
|
||||
FIELD(CAN1_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(I2C0_REF_CTRL, 0x140)
|
||||
FIELD(I2C0_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(I2C1_REF_CTRL, 0x144)
|
||||
FIELD(I2C1_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(DBG_LPD_CTRL, 0x148)
|
||||
FIELD(DBG_LPD_CTRL, CLKACT, 25, 1)
|
||||
FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3)
|
||||
REG32(TIMESTAMP_REF_CTRL, 0x14c)
|
||||
FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(CRL_SAFETY_CHK, 0x150)
|
||||
REG32(PSM_REF_CTRL, 0x154)
|
||||
FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(PSM_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(DBG_TSTMP_CTRL, 0x158)
|
||||
FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1)
|
||||
FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
|
||||
REG32(CPM_TOPSW_REF_CTRL, 0x15c)
|
||||
FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(USB3_DUAL_REF_CTRL, 0x160)
|
||||
FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1)
|
||||
FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10)
|
||||
FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3)
|
||||
REG32(RST_CPU_R5, 0x300)
|
||||
FIELD(RST_CPU_R5, RESET_PGE, 4, 1)
|
||||
FIELD(RST_CPU_R5, RESET_AMBA, 2, 1)
|
||||
FIELD(RST_CPU_R5, RESET_CPU1, 1, 1)
|
||||
FIELD(RST_CPU_R5, RESET_CPU0, 0, 1)
|
||||
REG32(RST_ADMA, 0x304)
|
||||
FIELD(RST_ADMA, RESET, 0, 1)
|
||||
REG32(RST_GEM0, 0x308)
|
||||
FIELD(RST_GEM0, RESET, 0, 1)
|
||||
REG32(RST_GEM1, 0x30c)
|
||||
FIELD(RST_GEM1, RESET, 0, 1)
|
||||
REG32(RST_SPARE, 0x310)
|
||||
FIELD(RST_SPARE, RESET, 0, 1)
|
||||
REG32(RST_USB0, 0x314)
|
||||
FIELD(RST_USB0, RESET, 0, 1)
|
||||
REG32(RST_UART0, 0x318)
|
||||
FIELD(RST_UART0, RESET, 0, 1)
|
||||
REG32(RST_UART1, 0x31c)
|
||||
FIELD(RST_UART1, RESET, 0, 1)
|
||||
REG32(RST_SPI0, 0x320)
|
||||
FIELD(RST_SPI0, RESET, 0, 1)
|
||||
REG32(RST_SPI1, 0x324)
|
||||
FIELD(RST_SPI1, RESET, 0, 1)
|
||||
REG32(RST_CAN0, 0x328)
|
||||
FIELD(RST_CAN0, RESET, 0, 1)
|
||||
REG32(RST_CAN1, 0x32c)
|
||||
FIELD(RST_CAN1, RESET, 0, 1)
|
||||
REG32(RST_I2C0, 0x330)
|
||||
FIELD(RST_I2C0, RESET, 0, 1)
|
||||
REG32(RST_I2C1, 0x334)
|
||||
FIELD(RST_I2C1, RESET, 0, 1)
|
||||
REG32(RST_DBG_LPD, 0x338)
|
||||
FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1)
|
||||
FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1)
|
||||
FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1)
|
||||
FIELD(RST_DBG_LPD, RESET, 0, 1)
|
||||
REG32(RST_GPIO, 0x33c)
|
||||
FIELD(RST_GPIO, RESET, 0, 1)
|
||||
REG32(RST_TTC, 0x344)
|
||||
FIELD(RST_TTC, TTC3_RESET, 3, 1)
|
||||
FIELD(RST_TTC, TTC2_RESET, 2, 1)
|
||||
FIELD(RST_TTC, TTC1_RESET, 1, 1)
|
||||
FIELD(RST_TTC, TTC0_RESET, 0, 1)
|
||||
REG32(RST_TIMESTAMP, 0x348)
|
||||
FIELD(RST_TIMESTAMP, RESET, 0, 1)
|
||||
REG32(RST_SWDT, 0x34c)
|
||||
FIELD(RST_SWDT, RESET, 0, 1)
|
||||
REG32(RST_OCM, 0x350)
|
||||
FIELD(RST_OCM, RESET, 0, 1)
|
||||
REG32(RST_IPI, 0x354)
|
||||
FIELD(RST_IPI, RESET, 0, 1)
|
||||
REG32(RST_SYSMON, 0x358)
|
||||
FIELD(RST_SYSMON, SEQ_RST, 1, 1)
|
||||
FIELD(RST_SYSMON, CFG_RST, 0, 1)
|
||||
REG32(RST_FPD, 0x360)
|
||||
FIELD(RST_FPD, SRST, 1, 1)
|
||||
FIELD(RST_FPD, POR, 0, 1)
|
||||
REG32(PSM_RST_MODE, 0x370)
|
||||
FIELD(PSM_RST_MODE, WAKEUP, 2, 1)
|
||||
FIELD(PSM_RST_MODE, RST_MODE, 0, 2)
|
||||
|
||||
#define CRL_R_MAX (R_PSM_RST_MODE + 1)
|
||||
|
||||
#define RPU_MAX_CPU 2
|
||||
|
||||
struct XlnxVersalCRL {
|
||||
SysBusDevice parent_obj;
|
||||
qemu_irq irq;
|
||||
|
||||
struct {
|
||||
ARMCPU *cpu_r5[RPU_MAX_CPU];
|
||||
DeviceState *adma[8];
|
||||
DeviceState *uart[2];
|
||||
DeviceState *gem[2];
|
||||
DeviceState *usb;
|
||||
} cfg;
|
||||
|
||||
RegisterInfoArray *reg_array;
|
||||
uint32_t regs[CRL_R_MAX];
|
||||
RegisterInfo regs_info[CRL_R_MAX];
|
||||
};
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user