target/riscv: Implement second stage MMU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Alistair Francis
Palmer Dabbelt
parent
1448689c7b
commit
36a18664ba
@ -104,6 +104,7 @@ struct CPURISCVState {
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target_ulong frm;
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target_ulong badaddr;
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target_ulong guest_phys_fault_addr;
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target_ulong priv_ver;
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target_ulong misa;
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@ -285,11 +285,12 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
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* @mmu_idx: Indicates current privilege level
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* @first_stage: Are we in first stage translation?
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* Second stage is used for hypervisor guest translation
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* @two_stage: Are we going to perform two stage translation
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*/
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static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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int *prot, target_ulong addr,
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int access_type, int mmu_idx,
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bool first_stage)
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bool first_stage, bool two_stage)
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{
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/* NOTE: the env->pc value visible here will not be
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* correct, but the value visible to the exception handler
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@ -297,12 +298,39 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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MemTxResult res;
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MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
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int mode = mmu_idx;
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bool use_background = false;
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/*
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* Check if we should use the background registers for the two
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* stage translation. We don't need to check if we actually need
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* two stage translation as that happened before this function
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* was called. Background registers will be used if the guest has
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* forced a two stage translation to be on (in HS or M mode).
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*/
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if (mode == PRV_M && access_type != MMU_INST_FETCH) {
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if (get_field(env->mstatus, MSTATUS_MPRV)) {
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mode = get_field(env->mstatus, MSTATUS_MPP);
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if (riscv_has_ext(env, RVH) &&
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get_field(env->mstatus, MSTATUS_MPV)) {
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use_background = true;
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}
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}
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}
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if (mode == PRV_S && access_type != MMU_INST_FETCH &&
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riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
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if (get_field(env->hstatus, HSTATUS_SPRV)) {
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mode = get_field(env->mstatus, SSTATUS_SPP);
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use_background = true;
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}
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}
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if (first_stage == false) {
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/* We are in stage 2 translation, this is similar to stage 1. */
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/* Stage 2 is always taken as U-mode */
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mode = PRV_U;
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}
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if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
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*physical = addr;
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@ -313,13 +341,30 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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*prot = 0;
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hwaddr base;
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int levels, ptidxbits, ptesize, vm, sum;
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int mxr = get_field(env->mstatus, MSTATUS_MXR);
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int levels, ptidxbits, ptesize, vm, sum, mxr, widened;
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if (first_stage == true) {
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mxr = get_field(env->mstatus, MSTATUS_MXR);
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} else {
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mxr = get_field(env->vsstatus, MSTATUS_MXR);
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}
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if (env->priv_ver >= PRIV_VERSION_1_10_0) {
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if (first_stage == true) {
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if (use_background) {
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base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
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vm = get_field(env->vsatp, SATP_MODE);
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} else {
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base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
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sum = get_field(env->mstatus, MSTATUS_SUM);
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vm = get_field(env->satp, SATP_MODE);
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}
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widened = 0;
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} else {
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base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
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vm = get_field(env->hgatp, HGATP_MODE);
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widened = 2;
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}
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sum = get_field(env->mstatus, MSTATUS_SUM);
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switch (vm) {
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case VM_1_10_SV32:
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levels = 2; ptidxbits = 10; ptesize = 4; break;
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@ -337,6 +382,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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g_assert_not_reached();
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}
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} else {
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widened = 0;
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base = (hwaddr)(env->sptbr) << PGSHIFT;
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sum = !get_field(env->mstatus, MSTATUS_PUM);
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vm = get_field(env->mstatus, MSTATUS_VM);
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@ -357,9 +403,16 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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}
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CPUState *cs = env_cpu(env);
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int va_bits = PGSHIFT + levels * ptidxbits;
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target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
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target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask;
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int va_bits = PGSHIFT + levels * ptidxbits + widened;
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target_ulong mask, masked_msbs;
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if (TARGET_LONG_BITS > (va_bits - 1)) {
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mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
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} else {
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mask = 0;
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}
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masked_msbs = (addr >> (va_bits - 1)) & mask;
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if (masked_msbs != 0 && masked_msbs != mask) {
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return TRANSLATE_FAIL;
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}
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@ -371,11 +424,29 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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restart:
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#endif
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for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
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target_ulong idx = (addr >> (PGSHIFT + ptshift)) &
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target_ulong idx;
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if (i == 0) {
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idx = (addr >> (PGSHIFT + ptshift)) &
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((1 << (ptidxbits + widened)) - 1);
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} else {
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idx = (addr >> (PGSHIFT + ptshift)) &
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((1 << ptidxbits) - 1);
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}
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/* check that physical address of PTE is legal */
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hwaddr pte_addr = base + idx * ptesize;
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hwaddr pte_addr;
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if (two_stage && first_stage) {
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hwaddr vbase;
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/* Do the second stage translation on the base PTE address. */
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get_physical_address(env, &vbase, prot, base, access_type,
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mmu_idx, false, true);
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pte_addr = vbase + idx * ptesize;
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} else {
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pte_addr = base + idx * ptesize;
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}
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if (riscv_feature(env, RISCV_FEATURE_PMP) &&
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!pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
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@ -472,7 +543,12 @@ restart:
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/* for superpage mappings, make a fake leaf PTE for the TLB's
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benefit. */
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target_ulong vpn = addr >> PGSHIFT;
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if (i == 0) {
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*physical = (ppn | (vpn & ((1L << (ptshift + widened)) - 1))) <<
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PGSHIFT;
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} else {
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*physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT;
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}
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/* set permissions on the TLB entry */
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if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
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@ -531,14 +607,23 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
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hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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hwaddr phys_addr;
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int prot;
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int mmu_idx = cpu_mmu_index(&cpu->env, false);
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if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx,
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true)) {
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if (get_physical_address(env, &phys_addr, &prot, addr, 0, mmu_idx,
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true, riscv_cpu_virt_enabled(env))) {
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return -1;
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}
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if (riscv_cpu_virt_enabled(env)) {
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if (get_physical_address(env, &phys_addr, &prot, phys_addr,
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0, mmu_idx, false, true)) {
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return -1;
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}
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}
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return phys_addr;
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}
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@ -592,17 +677,37 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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#ifndef CONFIG_USER_ONLY
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vaddr im_address;
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hwaddr pa = 0;
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int prot;
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bool pmp_violation = false;
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bool m_mode_two_stage = false;
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bool hs_mode_two_stage = false;
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bool first_stage_error = true;
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int ret = TRANSLATE_FAIL;
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int mode = mmu_idx;
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env->guest_phys_fault_addr = 0;
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qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
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__func__, address, access_type, mmu_idx);
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ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx,
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true);
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/*
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* Determine if we are in M mode and MPRV is set or in HS mode and SPRV is
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* set and we want to access a virtulisation address.
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*/
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if (riscv_has_ext(env, RVH)) {
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m_mode_two_stage = env->priv == PRV_M &&
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access_type != MMU_INST_FETCH &&
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get_field(env->mstatus, MSTATUS_MPRV) &&
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get_field(env->mstatus, MSTATUS_MPV);
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hs_mode_two_stage = env->priv == PRV_S &&
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!riscv_cpu_virt_enabled(env) &&
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access_type != MMU_INST_FETCH &&
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get_field(env->hstatus, HSTATUS_SPRV) &&
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get_field(env->hstatus, HSTATUS_SPV);
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}
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if (mode == PRV_M && access_type != MMU_INST_FETCH) {
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if (get_field(env->mstatus, MSTATUS_MPRV)) {
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@ -610,9 +715,55 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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}
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}
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if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) {
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/* Two stage lookup */
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ret = get_physical_address(env, &pa, &prot, address, access_type,
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mmu_idx, true, true);
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qemu_log_mask(CPU_LOG_MMU,
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"%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
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" prot %d\n", __func__, address, ret, pa, prot);
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"%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
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TARGET_FMT_plx " prot %d\n",
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__func__, address, ret, pa, prot);
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if (ret != TRANSLATE_FAIL) {
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/* Second stage lookup */
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im_address = pa;
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ret = get_physical_address(env, &pa, &prot, im_address,
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access_type, mmu_idx, false, true);
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qemu_log_mask(CPU_LOG_MMU,
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"%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
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TARGET_FMT_plx " prot %d\n",
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__func__, im_address, ret, pa, prot);
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if (riscv_feature(env, RISCV_FEATURE_PMP) &&
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(ret == TRANSLATE_SUCCESS) &&
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!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
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ret = TRANSLATE_PMP_FAIL;
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}
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if (ret != TRANSLATE_SUCCESS) {
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/*
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* Guest physical address translation failed, this is a HS
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* level exception
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*/
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first_stage_error = false;
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env->guest_phys_fault_addr = (im_address |
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(address &
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(TARGET_PAGE_SIZE - 1))) >> 2;
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}
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}
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} else {
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/* Single stage lookup */
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ret = get_physical_address(env, &pa, &prot, address, access_type,
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mmu_idx, true, false);
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qemu_log_mask(CPU_LOG_MMU,
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"%s address=%" VADDR_PRIx " ret %d physical "
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TARGET_FMT_plx " prot %d\n",
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__func__, address, ret, pa, prot);
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}
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if (riscv_feature(env, RISCV_FEATURE_PMP) &&
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(ret == TRANSLATE_SUCCESS) &&
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@ -622,6 +773,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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if (ret == TRANSLATE_PMP_FAIL) {
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pmp_violation = true;
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}
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if (ret == TRANSLATE_SUCCESS) {
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tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
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prot, mmu_idx, TARGET_PAGE_SIZE);
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@ -629,9 +781,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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} else if (probe) {
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return false;
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} else {
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raise_mmu_exception(env, address, access_type, pmp_violation, true);
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raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error);
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riscv_raise_exception(env, cs->exception_index, retaddr);
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}
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return true;
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#else
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switch (access_type) {
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case MMU_INST_FETCH:
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