target/s390x: Fix LPSW
Currently LPSW does not invert the mask bit 12 and incorrectly copies the BA bit into the address. Fix by generating code similar to what s390_cpu_load_normal() does. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230315020408.384766-2-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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@ -2910,19 +2910,21 @@ static DisasJumpType op_lpp(DisasContext *s, DisasOps *o)
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static DisasJumpType op_lpsw(DisasContext *s, DisasOps *o)
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{
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TCGv_i64 t1, t2;
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TCGv_i64 mask, addr;
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per_breaking_event(s);
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t1 = tcg_temp_new_i64();
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t2 = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s),
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MO_TEUL | MO_ALIGN_8);
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tcg_gen_addi_i64(o->in2, o->in2, 4);
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tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
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/* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
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tcg_gen_shli_i64(t1, t1, 32);
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gen_helper_load_psw(cpu_env, t1, t2);
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/*
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* Convert the short PSW into the normal PSW, similar to what
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* s390_cpu_load_normal() does.
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*/
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mask = tcg_temp_new_i64();
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addr = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(mask, o->in2, get_mem_index(s), MO_TEUQ | MO_ALIGN_8);
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tcg_gen_andi_i64(addr, mask, PSW_MASK_SHORT_ADDR);
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tcg_gen_andi_i64(mask, mask, PSW_MASK_SHORT_CTRL);
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tcg_gen_xori_i64(mask, mask, PSW_MASK_SHORTPSW);
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gen_helper_load_psw(cpu_env, mask, addr);
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return DISAS_NORETURN;
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}
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