s390x/tcg: Use tcg_gen_gvec_bitsel for VECTOR SELECT
This replaces the target-specific implementations for VSEL. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
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@ -245,6 +245,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
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#define gen_gvec_fn_3(fn, es, v1, v2, v3) \
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tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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vec_full_reg_offset(v3), 16, 16)
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#define gen_gvec_fn_4(fn, es, v1, v2, v3, v4) \
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tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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vec_full_reg_offset(v3), vec_full_reg_offset(v4), 16, 16)
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/*
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* Helper to carry out a 128 bit vector computation using 2 i64 values per
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@ -915,40 +918,11 @@ static DisasJumpType op_vsce(DisasContext *s, DisasOps *o)
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return DISAS_NEXT;
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}
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static void gen_sel_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c)
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{
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TCGv_i64 t = tcg_temp_new_i64();
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/* bit in c not set -> copy bit from b */
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tcg_gen_andc_i64(t, b, c);
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/* bit in c set -> copy bit from a */
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tcg_gen_and_i64(d, a, c);
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/* merge the results */
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tcg_gen_or_i64(d, d, t);
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tcg_temp_free_i64(t);
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}
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static void gen_sel_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b,
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TCGv_vec c)
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{
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TCGv_vec t = tcg_temp_new_vec_matching(d);
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tcg_gen_andc_vec(vece, t, b, c);
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tcg_gen_and_vec(vece, d, a, c);
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tcg_gen_or_vec(vece, d, d, t);
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tcg_temp_free_vec(t);
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}
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static DisasJumpType op_vsel(DisasContext *s, DisasOps *o)
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{
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static const GVecGen4 gvec_op = {
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.fni8 = gen_sel_i64,
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.fniv = gen_sel_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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};
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gen_gvec_4(get_field(s->fields, v1), get_field(s->fields, v2),
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get_field(s->fields, v3), get_field(s->fields, v4), &gvec_op);
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gen_gvec_fn_4(bitsel, ES_8, get_field(s->fields, v1),
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get_field(s->fields, v4), get_field(s->fields, v2),
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get_field(s->fields, v3));
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return DISAS_NEXT;
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}
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