intel-iommu: Extend address width to 48 bits
The current implementation of Intel IOMMU code only supports 39 bits iova address width. This patch provides a new parameter (x-aw-bits) for intel-iommu to extend its address width to 48 bits but keeping the default the same (39 bits). The reason for not changing the default is to avoid potential compatibility problems with live migration of intel-iommu enabled QEMU guest. The only valid values for 'x-aw-bits' parameter are 39 and 48. After enabling larger address width (48), we should be able to map larger iova addresses in the guest. For example, a QEMU guest that is configured with large memory ( >=1TB ). To check whether 48 bits aw is enabled, we can grep in the guest dmesg output with line: "DMAR: Host address width 48". Signed-off-by: Prasad Singamsetty <prasad.singamsety@oracle.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Prasad Singamsetty
Michael S. Tsirkin
parent
92e5d85e83
commit
37f51384ae
@ -2473,6 +2473,7 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker)
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AcpiDmarDeviceScope *scope = NULL;
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/* Root complex IOAPIC use one path[0] only */
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size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
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IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
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assert(iommu);
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if (iommu->intr_supported) {
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@ -2480,7 +2481,7 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker)
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}
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dmar = acpi_data_push(table_data, sizeof(*dmar));
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dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
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dmar->host_address_width = intel_iommu->aw_bits - 1;
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dmar->flags = dmar_flags;
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/* DMAR Remapping Hardware Unit Definition structure */
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@ -521,9 +521,9 @@ static inline dma_addr_t vtd_ce_get_slpt_base(VTDContextEntry *ce)
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return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR;
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}
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static inline uint64_t vtd_get_slpte_addr(uint64_t slpte)
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static inline uint64_t vtd_get_slpte_addr(uint64_t slpte, uint8_t aw)
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{
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return slpte & VTD_SL_PT_BASE_ADDR_MASK(VTD_HOST_ADDRESS_WIDTH);
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return slpte & VTD_SL_PT_BASE_ADDR_MASK(aw);
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}
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/* Whether the pte indicates the address of the page frame */
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@ -608,20 +608,21 @@ static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu,
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return true;
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}
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static inline uint64_t vtd_iova_limit(VTDContextEntry *ce)
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static inline uint64_t vtd_iova_limit(VTDContextEntry *ce, uint8_t aw)
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{
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uint32_t ce_agaw = vtd_ce_get_agaw(ce);
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return 1ULL << MIN(ce_agaw, VTD_MGAW);
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return 1ULL << MIN(ce_agaw, aw);
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}
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/* Return true if IOVA passes range check, otherwise false. */
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static inline bool vtd_iova_range_check(uint64_t iova, VTDContextEntry *ce)
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static inline bool vtd_iova_range_check(uint64_t iova, VTDContextEntry *ce,
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uint8_t aw)
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{
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/*
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* Check if @iova is above 2^X-1, where X is the minimum of MGAW
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* in CAP_REG and AW in context-entry.
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*/
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return !(iova & ~(vtd_iova_limit(ce) - 1));
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return !(iova & ~(vtd_iova_limit(ce, aw) - 1));
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}
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/*
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@ -669,7 +670,7 @@ static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
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*/
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static int vtd_iova_to_slpte(VTDContextEntry *ce, uint64_t iova, bool is_write,
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uint64_t *slptep, uint32_t *slpte_level,
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bool *reads, bool *writes)
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bool *reads, bool *writes, uint8_t aw_bits)
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{
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dma_addr_t addr = vtd_ce_get_slpt_base(ce);
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uint32_t level = vtd_ce_get_level(ce);
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@ -677,7 +678,7 @@ static int vtd_iova_to_slpte(VTDContextEntry *ce, uint64_t iova, bool is_write,
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uint64_t slpte;
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uint64_t access_right_check;
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if (!vtd_iova_range_check(iova, ce)) {
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if (!vtd_iova_range_check(iova, ce, aw_bits)) {
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trace_vtd_err_dmar_iova_overflow(iova);
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return -VTD_FR_ADDR_BEYOND_MGAW;
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}
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@ -714,7 +715,7 @@ static int vtd_iova_to_slpte(VTDContextEntry *ce, uint64_t iova, bool is_write,
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*slpte_level = level;
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return 0;
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}
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addr = vtd_get_slpte_addr(slpte);
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addr = vtd_get_slpte_addr(slpte, aw_bits);
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level--;
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}
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}
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@ -732,11 +733,12 @@ typedef int (*vtd_page_walk_hook)(IOMMUTLBEntry *entry, void *private);
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* @read: whether parent level has read permission
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* @write: whether parent level has write permission
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* @notify_unmap: whether we should notify invalid entries
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* @aw: maximum address width
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*/
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static int vtd_page_walk_level(dma_addr_t addr, uint64_t start,
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uint64_t end, vtd_page_walk_hook hook_fn,
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void *private, uint32_t level,
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bool read, bool write, bool notify_unmap)
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void *private, uint32_t level, bool read,
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bool write, bool notify_unmap, uint8_t aw)
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{
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bool read_cur, write_cur, entry_valid;
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uint32_t offset;
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@ -783,7 +785,7 @@ static int vtd_page_walk_level(dma_addr_t addr, uint64_t start,
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entry.target_as = &address_space_memory;
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entry.iova = iova & subpage_mask;
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/* NOTE: this is only meaningful if entry_valid == true */
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entry.translated_addr = vtd_get_slpte_addr(slpte);
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entry.translated_addr = vtd_get_slpte_addr(slpte, aw);
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entry.addr_mask = ~subpage_mask;
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entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur);
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if (!entry_valid && !notify_unmap) {
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@ -803,10 +805,10 @@ static int vtd_page_walk_level(dma_addr_t addr, uint64_t start,
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trace_vtd_page_walk_skip_perm(iova, iova_next);
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goto next;
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}
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ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte), iova,
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ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte, aw), iova,
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MIN(iova_next, end), hook_fn, private,
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level - 1, read_cur, write_cur,
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notify_unmap);
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notify_unmap, aw);
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if (ret < 0) {
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return ret;
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}
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@ -827,25 +829,26 @@ next:
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* @end: IOVA range end address (start <= addr < end)
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* @hook_fn: the hook that to be called for each detected area
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* @private: private data for the hook function
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* @aw: maximum address width
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*/
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static int vtd_page_walk(VTDContextEntry *ce, uint64_t start, uint64_t end,
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vtd_page_walk_hook hook_fn, void *private,
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bool notify_unmap)
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bool notify_unmap, uint8_t aw)
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{
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dma_addr_t addr = vtd_ce_get_slpt_base(ce);
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uint32_t level = vtd_ce_get_level(ce);
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if (!vtd_iova_range_check(start, ce)) {
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if (!vtd_iova_range_check(start, ce, aw)) {
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return -VTD_FR_ADDR_BEYOND_MGAW;
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}
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if (!vtd_iova_range_check(end, ce)) {
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if (!vtd_iova_range_check(end, ce, aw)) {
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/* Fix end so that it reaches the maximum */
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end = vtd_iova_limit(ce);
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end = vtd_iova_limit(ce, aw);
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}
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return vtd_page_walk_level(addr, start, end, hook_fn, private,
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level, true, true, notify_unmap);
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level, true, true, notify_unmap, aw);
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}
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/* Map a device to its corresponding domain (context-entry) */
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@ -867,7 +870,7 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
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return -VTD_FR_ROOT_ENTRY_P;
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}
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if (re.rsvd || (re.val & VTD_ROOT_ENTRY_RSVD(VTD_HOST_ADDRESS_WIDTH))) {
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if (re.rsvd || (re.val & VTD_ROOT_ENTRY_RSVD(s->aw_bits))) {
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trace_vtd_re_invalid(re.rsvd, re.val);
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return -VTD_FR_ROOT_ENTRY_RSVD;
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}
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@ -884,7 +887,7 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
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}
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if ((ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI) ||
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(ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO(VTD_HOST_ADDRESS_WIDTH))) {
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(ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO(s->aw_bits))) {
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trace_vtd_ce_invalid(ce->hi, ce->lo);
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return -VTD_FR_CONTEXT_ENTRY_RSVD;
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}
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@ -1166,7 +1169,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
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}
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ret_fr = vtd_iova_to_slpte(&ce, addr, is_write, &slpte, &level,
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&reads, &writes);
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&reads, &writes, s->aw_bits);
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if (ret_fr) {
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ret_fr = -ret_fr;
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if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
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@ -1183,7 +1186,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
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access_flags, level);
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out:
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entry->iova = addr & page_mask;
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entry->translated_addr = vtd_get_slpte_addr(slpte) & page_mask;
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entry->translated_addr = vtd_get_slpte_addr(slpte, s->aw_bits) & page_mask;
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entry->addr_mask = ~page_mask;
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entry->perm = access_flags;
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return true;
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@ -1200,7 +1203,7 @@ static void vtd_root_table_setup(IntelIOMMUState *s)
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{
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s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
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s->root_extended = s->root & VTD_RTADDR_RTT;
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s->root &= VTD_RTADDR_ADDR_MASK(VTD_HOST_ADDRESS_WIDTH);
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s->root &= VTD_RTADDR_ADDR_MASK(s->aw_bits);
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trace_vtd_reg_dmar_root(s->root, s->root_extended);
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}
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@ -1216,7 +1219,7 @@ static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s)
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uint64_t value = 0;
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value = vtd_get_quad_raw(s, DMAR_IRTA_REG);
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s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1);
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s->intr_root = value & VTD_IRTA_ADDR_MASK(VTD_HOST_ADDRESS_WIDTH);
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s->intr_root = value & VTD_IRTA_ADDR_MASK(s->aw_bits);
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s->intr_eime = value & VTD_IRTA_EIME;
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/* Notify global invalidation */
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@ -1392,7 +1395,7 @@ static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
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if (!ret && domain_id == VTD_CONTEXT_ENTRY_DID(ce.hi)) {
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vtd_page_walk(&ce, addr, addr + (1 << am) * VTD_PAGE_SIZE,
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vtd_page_invalidate_notify_hook,
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(void *)&vtd_as->iommu, true);
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(void *)&vtd_as->iommu, true, s->aw_bits);
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}
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}
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}
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@ -1472,7 +1475,7 @@ static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en)
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trace_vtd_inv_qi_enable(en);
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if (en) {
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s->iq = iqa_val & VTD_IQA_IQA_MASK(VTD_HOST_ADDRESS_WIDTH);
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s->iq = iqa_val & VTD_IQA_IQA_MASK(s->aw_bits);
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/* 2^(x+8) entries */
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s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8);
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s->qi_enabled = true;
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@ -2403,6 +2406,8 @@ static Property vtd_properties[] = {
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DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim,
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ON_OFF_AUTO_AUTO),
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DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false),
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DEFINE_PROP_UINT8("x-aw-bits", IntelIOMMUState, aw_bits,
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VTD_HOST_ADDRESS_WIDTH),
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DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -2758,6 +2763,7 @@ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
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hwaddr size;
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hwaddr start = n->start;
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hwaddr end = n->end;
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IntelIOMMUState *s = as->iommu_state;
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/*
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* Note: all the codes in this function has a assumption that IOVA
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@ -2765,12 +2771,12 @@ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
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* VT-d spec), otherwise we need to consider overflow of 64 bits.
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*/
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if (end > VTD_ADDRESS_SIZE(VTD_HOST_ADDRESS_WIDTH)) {
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if (end > VTD_ADDRESS_SIZE(s->aw_bits)) {
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/*
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* Don't need to unmap regions that is bigger than the whole
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* VT-d supported address space size
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*/
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end = VTD_ADDRESS_SIZE(VTD_HOST_ADDRESS_WIDTH);
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end = VTD_ADDRESS_SIZE(s->aw_bits);
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}
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assert(start <= end);
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@ -2782,9 +2788,9 @@ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
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* suite the minimum available mask.
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*/
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int n = 64 - clz64(size);
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if (n > VTD_MGAW) {
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if (n > s->aw_bits) {
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/* should not happen, but in case it happens, limit it */
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n = VTD_MGAW;
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n = s->aw_bits;
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}
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size = 1ULL << n;
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}
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@ -2844,7 +2850,8 @@ static void vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
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PCI_FUNC(vtd_as->devfn),
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VTD_CONTEXT_ENTRY_DID(ce.hi),
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ce.hi, ce.lo);
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vtd_page_walk(&ce, 0, ~0ULL, vtd_replay_hook, (void *)n, false);
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vtd_page_walk(&ce, 0, ~0ULL, vtd_replay_hook, (void *)n, false,
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s->aw_bits);
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} else {
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trace_vtd_replay_ce_invalid(bus_n, PCI_SLOT(vtd_as->devfn),
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PCI_FUNC(vtd_as->devfn));
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@ -2859,7 +2866,6 @@ static void vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
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static void vtd_init(IntelIOMMUState *s)
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{
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X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
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uint8_t aw_bits = VTD_HOST_ADDRESS_WIDTH;
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memset(s->csr, 0, DMAR_REG_SIZE);
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memset(s->wmask, 0, DMAR_REG_SIZE);
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@ -2878,21 +2884,24 @@ static void vtd_init(IntelIOMMUState *s)
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s->next_frcd_reg = 0;
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s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND |
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VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS |
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VTD_CAP_SAGAW_39bit | VTD_CAP_MGAW(VTD_HOST_ADDRESS_WIDTH);
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VTD_CAP_SAGAW_39bit | VTD_CAP_MGAW(s->aw_bits);
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if (s->aw_bits == VTD_HOST_AW_48BIT) {
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s->cap |= VTD_CAP_SAGAW_48bit;
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}
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s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
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/*
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* Rsvd field masks for spte
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*/
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vtd_paging_entry_rsvd_field[0] = ~0ULL;
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vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(aw_bits);
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vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(aw_bits);
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vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(aw_bits);
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vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(aw_bits);
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vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(aw_bits);
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vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(aw_bits);
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vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(aw_bits);
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vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(aw_bits);
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vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
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if (x86_iommu->intr_supported) {
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s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
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@ -3029,6 +3038,14 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
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}
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}
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/* Currently only address widths supported are 39 and 48 bits */
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if ((s->aw_bits != VTD_HOST_AW_39BIT) &&
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(s->aw_bits != VTD_HOST_AW_48BIT)) {
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error_setg(errp, "Supported values for x-aw-bits are: %d, %d",
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VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
@ -131,7 +131,7 @@
|
||||
#define VTD_TLB_DID(val) (((val) >> 32) & VTD_DOMAIN_ID_MASK)
|
||||
|
||||
/* IVA_REG */
|
||||
#define VTD_IVA_ADDR(val) ((val) & ~0xfffULL & ((1ULL << VTD_MGAW) - 1))
|
||||
#define VTD_IVA_ADDR(val) ((val) & ~0xfffULL)
|
||||
#define VTD_IVA_AM(val) ((val) & 0x3fULL)
|
||||
|
||||
/* GCMD_REG */
|
||||
@ -197,7 +197,6 @@
|
||||
#define VTD_DOMAIN_ID_SHIFT 16 /* 16-bit domain id for 64K domains */
|
||||
#define VTD_DOMAIN_ID_MASK ((1UL << VTD_DOMAIN_ID_SHIFT) - 1)
|
||||
#define VTD_CAP_ND (((VTD_DOMAIN_ID_SHIFT - 4) / 2) & 7ULL)
|
||||
#define VTD_MGAW 39 /* Maximum Guest Address Width */
|
||||
#define VTD_ADDRESS_SIZE(aw) (1ULL << (aw))
|
||||
#define VTD_CAP_MGAW(aw) ((((aw) - 1) & 0x3fULL) << 16)
|
||||
#define VTD_MAMV 18ULL
|
||||
@ -213,7 +212,6 @@
|
||||
#define VTD_CAP_SAGAW_39bit (0x2ULL << VTD_CAP_SAGAW_SHIFT)
|
||||
/* 48-bit AGAW, 4-level page-table */
|
||||
#define VTD_CAP_SAGAW_48bit (0x4ULL << VTD_CAP_SAGAW_SHIFT)
|
||||
#define VTD_CAP_SAGAW VTD_CAP_SAGAW_39bit
|
||||
|
||||
/* IQT_REG */
|
||||
#define VTD_IQT_QT(val) (((val) >> 4) & 0x7fffULL)
|
||||
@ -252,7 +250,7 @@
|
||||
#define VTD_FRCD_SID_MASK 0xffffULL
|
||||
#define VTD_FRCD_SID(val) ((val) & VTD_FRCD_SID_MASK)
|
||||
/* For the low 64-bit of 128-bit */
|
||||
#define VTD_FRCD_FI(val) ((val) & (((1ULL << VTD_MGAW) - 1) ^ 0xfffULL))
|
||||
#define VTD_FRCD_FI(val) ((val) & ~0xfffULL)
|
||||
|
||||
/* DMA Remapping Fault Conditions */
|
||||
typedef enum VTDFaultReason {
|
||||
@ -360,8 +358,7 @@ typedef union VTDInvDesc VTDInvDesc;
|
||||
#define VTD_INV_DESC_IOTLB_DOMAIN (2ULL << 4)
|
||||
#define VTD_INV_DESC_IOTLB_PAGE (3ULL << 4)
|
||||
#define VTD_INV_DESC_IOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
|
||||
#define VTD_INV_DESC_IOTLB_ADDR(val) ((val) & ~0xfffULL & \
|
||||
((1ULL << VTD_MGAW) - 1))
|
||||
#define VTD_INV_DESC_IOTLB_ADDR(val) ((val) & ~0xfffULL)
|
||||
#define VTD_INV_DESC_IOTLB_AM(val) ((val) & 0x3fULL)
|
||||
#define VTD_INV_DESC_IOTLB_RSVD_LO 0xffffffff0000ff00ULL
|
||||
#define VTD_INV_DESC_IOTLB_RSVD_HI 0xf80ULL
|
||||
|
||||
@ -304,6 +304,7 @@ struct IntelIOMMUState {
|
||||
bool intr_eime; /* Extended interrupt mode enabled */
|
||||
OnOffAuto intr_eim; /* Toggle for EIM cabability */
|
||||
bool buggy_eim; /* Force buggy EIM unless eim=off */
|
||||
uint8_t aw_bits; /* Host/IOVA address width (in bits) */
|
||||
};
|
||||
|
||||
/* Find the VTD Address space associated with the given bus pointer,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user