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MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registers 

are implemented.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2589 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-04-02 17:28:07 +00:00
parent 7524c84d82
commit 38121543c7
1 changed files with 9 additions and 2 deletions
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11
target-mips/translate.c
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@ -1375,7 +1375,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
if (ctx->hflags & MIPS_HFLAG_BMASK) {
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile,
"undefined branch in delay slot at pc 0x%08x\n", ctx->pc);
"undefined branch in delay slot at PC " TARGET_FMT_lx "\n",
ctx->pc);
}
MIPS_INVAL("branch/jump in bdelay slot");
generate_exception(ctx, EXCP_RI);
@ -4841,9 +4842,15 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
}
GEN_STORE_TN_REG(rt, T0);
break;
/* Shadow registers (not implemented). */
case OPC_RDPGPR:
case OPC_WRPGPR:
if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) {
/* Shadow registers not implemented. */
GEN_LOAD_REG_TN(T0, rt);
GEN_STORE_TN_REG(rd, T0);
} else
generate_exception(ctx, EXCP_RI);
break;
default:
generate_exception(ctx, EXCP_RI);
break;