sh7750: convert memory controller/ioport to memory API
Signed-off-by: Benoit Canet <benoit.canet@gmail.com> Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
parent
a3d12d073e
commit
382863e2c6
2
hw/r2d.c
2
hw/r2d.c
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@ -250,7 +250,7 @@ static void r2d_init(ram_addr_t ram_size,
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memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE);
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memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
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/* Register peripherals */
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s = sh7750_init(env);
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s = sh7750_init(env, address_space_mem);
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irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
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sysbus_create_varargs("sh_pci", 0x1e200000, irq[PCI_INTA], irq[PCI_INTB],
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irq[PCI_INTC], irq[PCI_INTD], NULL);
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3
hw/sh.h
3
hw/sh.h
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@ -9,8 +9,9 @@
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/* sh7750.c */
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struct SH7750State;
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struct MemoryRegion;
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struct SH7750State *sh7750_init(CPUState * cpu);
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struct SH7750State *sh7750_init(CPUState * cpu, struct MemoryRegion *sysmem);
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typedef struct {
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/* The callback will be triggered if any of the designated lines change */
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72
hw/sh7750.c
72
hw/sh7750.c
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@ -30,10 +30,18 @@
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#include "sh7750_regnames.h"
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#include "sh_intc.h"
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#include "cpu.h"
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#include "exec-memory.h"
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#define NB_DEVICES 4
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typedef struct SH7750State {
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MemoryRegion iomem;
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MemoryRegion iomem_1f0;
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MemoryRegion iomem_ff0;
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MemoryRegion iomem_1f8;
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MemoryRegion iomem_ff8;
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MemoryRegion iomem_1fc;
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MemoryRegion iomem_ffc;
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/* CPU */
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CPUSH4State *cpu;
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/* Peripheral frequency in Hz */
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@ -436,16 +444,16 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
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}
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}
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static CPUReadMemoryFunc * const sh7750_mem_read[] = {
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sh7750_mem_readb,
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sh7750_mem_readw,
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sh7750_mem_readl
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};
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static CPUWriteMemoryFunc * const sh7750_mem_write[] = {
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sh7750_mem_writeb,
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sh7750_mem_writew,
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sh7750_mem_writel
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static const MemoryRegionOps sh7750_mem_ops = {
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.old_mmio = {
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.read = {sh7750_mem_readb,
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sh7750_mem_readw,
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sh7750_mem_readl },
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.write = {sh7750_mem_writeb,
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sh7750_mem_writew,
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sh7750_mem_writel },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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/* sh775x interrupt controller tables for sh_intc.c
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@ -706,30 +714,40 @@ static CPUWriteMemoryFunc * const sh7750_mmct_write[] = {
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sh7750_mmct_writel
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};
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SH7750State *sh7750_init(CPUSH4State * cpu)
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SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
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{
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SH7750State *s;
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int sh7750_io_memory;
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int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
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s = g_malloc0(sizeof(SH7750State));
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s->cpu = cpu;
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s->periph_freq = 60000000; /* 60MHz */
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sh7750_io_memory = cpu_register_io_memory(sh7750_mem_read,
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sh7750_mem_write, s,
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DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory_offset(0x1f000000, 0x1000,
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sh7750_io_memory, 0x1f000000);
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cpu_register_physical_memory_offset(0xff000000, 0x1000,
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sh7750_io_memory, 0x1f000000);
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cpu_register_physical_memory_offset(0x1f800000, 0x1000,
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sh7750_io_memory, 0x1f800000);
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cpu_register_physical_memory_offset(0xff800000, 0x1000,
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sh7750_io_memory, 0x1f800000);
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cpu_register_physical_memory_offset(0x1fc00000, 0x1000,
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sh7750_io_memory, 0x1fc00000);
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cpu_register_physical_memory_offset(0xffc00000, 0x1000,
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sh7750_io_memory, 0x1fc00000);
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memory_region_init_io(&s->iomem, &sh7750_mem_ops, s,
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"memory", 0x1fc01000);
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memory_region_init_alias(&s->iomem_1f0, "memory-1f0",
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&s->iomem, 0x1f000000, 0x1000);
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memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0);
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memory_region_init_alias(&s->iomem_ff0, "memory-ff0",
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&s->iomem, 0x1f000000, 0x1000);
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memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0);
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memory_region_init_alias(&s->iomem_1f8, "memory-1f8",
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&s->iomem, 0x1f800000, 0x1000);
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memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8);
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memory_region_init_alias(&s->iomem_ff8, "memory-ff8",
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&s->iomem, 0x1f800000, 0x1000);
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memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8);
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memory_region_init_alias(&s->iomem_1fc, "memory-1fc",
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&s->iomem, 0x1fc00000, 0x1000);
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memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc);
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memory_region_init_alias(&s->iomem_ffc, "memory-ffc",
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&s->iomem, 0x1fc00000, 0x1000);
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memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc);
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sh7750_mm_cache_and_tlb = cpu_register_io_memory(sh7750_mmct_read,
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sh7750_mmct_write, s,
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