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target-ppc: Introduce callback for interrupt endianness

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POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR
special purpose register to decide the endianness to use when
entering interrupt handlers. When running a Linux guest, this
provides a hint on the endianness used by the kernel. And when
it comes to dumping a guest, the information is needed to write
ELF headers using the kernel endianness.

Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
[agraf: change subject line]
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Greg Kurz 2014-05-19 19:59:05 +02:00 committed by Alexander Graf
parent 0c967de9c0
commit 382d2db62b
2 changed files with 17 additions and 0 deletions
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1
target-ppc/cpu-qom.h
View File

@ -76,6 +76,7 @@ typedef struct PowerPCCPUClass {
int (*handle_mmu_fault)(PowerPCCPU *cpu, target_ulong eaddr, int rwx, int (*handle_mmu_fault)(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
int mmu_idx); int mmu_idx);
#endif #endif
bool (*interrupts_big_endian)(PowerPCCPU *cpu);
} PowerPCCPUClass; } PowerPCCPUClass;
/** /**

16
target-ppc/translate_init.c
View File

@ -3111,6 +3111,18 @@ static int check_pow_hid0_74xx (CPUPPCState *env)
return 0; return 0;
} }
static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
{
return true;
}
#ifdef TARGET_PPC64
static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
{
return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
}
#endif
/*****************************************************************************/ /*****************************************************************************/
/* PowerPC implementations definitions */ /* PowerPC implementations definitions */
@ -7803,6 +7815,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
POWERPC_FLAG_VSX; POWERPC_FLAG_VSX;
pcc->l1_dcache_size = 0x8000; pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000; pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
} }
POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data) POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
@ -7861,6 +7874,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
POWERPC_FLAG_VSX; POWERPC_FLAG_VSX;
pcc->l1_dcache_size = 0x8000; pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000; pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
} }
static void init_proc_POWER8(CPUPPCState *env) static void init_proc_POWER8(CPUPPCState *env)
@ -7933,6 +7947,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
POWERPC_FLAG_VSX; POWERPC_FLAG_VSX;
pcc->l1_dcache_size = 0x8000; pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000; pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
} }
#endif /* defined (TARGET_PPC64) */ #endif /* defined (TARGET_PPC64) */
@ -9259,6 +9274,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
pcc->parent_realize = dc->realize; pcc->parent_realize = dc->realize;
pcc->pvr = CPU_POWERPC_DEFAULT_MASK; pcc->pvr = CPU_POWERPC_DEFAULT_MASK;
pcc->pvr_mask = CPU_POWERPC_DEFAULT_MASK; pcc->pvr_mask = CPU_POWERPC_DEFAULT_MASK;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
dc->realize = ppc_cpu_realizefn; dc->realize = ppc_cpu_realizefn;
dc->unrealize = ppc_cpu_unrealizefn; dc->unrealize = ppc_cpu_unrealizefn;