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target/ppc/mmu: Use LPCR:HR to chose radix vs. hash translation

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Now that LPCR:HR is set properly for SPAPR, use it for deciding
the translation type, which also works for bare metal

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190215170029.15641-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Benjamin Herrenschmidt 2019-02-15 18:00:19 +01:00 committed by David Gibson
parent 00fd075e18
commit 38c784a1cc
3 changed files with 21 additions and 13 deletions
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11
target/ppc/mmu-book3s-v3.c
View File

@ -26,9 +26,18 @@
int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
int mmu_idx) int mmu_idx)
{ {
if (ppc64_radix_guest(cpu)) { /* Guest uses radix */ if (ppc64_v3_radix(cpu)) { /* Guest uses radix */
return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx); return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
} else { /* Guest uses hash */ } else { /* Guest uses hash */
return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx); return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
} }
} }
hwaddr ppc64_v3_get_phys_page_debug(PowerPCCPU *cpu, vaddr eaddr)
{
if (ppc64_v3_radix(cpu)) {
return ppc_radix64_get_phys_page_debug(cpu, eaddr);
} else {
return ppc_hash64_get_phys_page_debug(cpu, eaddr);
}
}

14
target/ppc/mmu-book3s-v3.h
View File

@ -43,14 +43,18 @@ static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT); return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
} }
static inline bool ppc64_radix_guest(PowerPCCPU *cpu) /*
* The LPCR:HR bit is a shortcut that avoids having to
* dig out the partition table in the fast path. This is
* also how the HW uses it.
*/
static inline bool ppc64_v3_radix(PowerPCCPU *cpu)
{ {
PPCVirtualHypervisorClass *vhc = return !!(cpu->env.spr[SPR_LPCR] & LPCR_HR);
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
} }
hwaddr ppc64_v3_get_phys_page_debug(PowerPCCPU *cpu, vaddr eaddr);
int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
int mmu_idx); int mmu_idx);

9
target/ppc/mmu_helper.c
View File

@ -1342,7 +1342,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env)); dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
break; break;
case POWERPC_MMU_3_00: case POWERPC_MMU_3_00:
if (ppc64_radix_guest(ppc_env_get_cpu(env))) { if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
/* TODO - Unsupported */ /* TODO - Unsupported */
} else { } else {
dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env)); dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
@ -1489,12 +1489,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
case POWERPC_MMU_2_07: case POWERPC_MMU_2_07:
return ppc_hash64_get_phys_page_debug(cpu, addr); return ppc_hash64_get_phys_page_debug(cpu, addr);
case POWERPC_MMU_3_00: case POWERPC_MMU_3_00:
if (ppc64_radix_guest(ppc_env_get_cpu(env))) { return ppc64_v3_get_phys_page_debug(cpu, addr);
return ppc_radix64_get_phys_page_debug(cpu, addr);
} else {
return ppc_hash64_get_phys_page_debug(cpu, addr);
}
break;
#endif #endif
case POWERPC_MMU_32B: case POWERPC_MMU_32B: