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target/ppc: fix xscvqpdp register access

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This instruction has VRT and VRB fields instead of T/TX and B/BX.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211213120958.24443-4-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst 2021-12-17 17:57:18 +01:00 committed by Cédric Le Goater
parent c5df1898a1
commit 38d4914c50
1 changed files with 3 additions and 2 deletions
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5
target/ppc/translate/vsx-impl.c.inc
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@ -913,8 +913,9 @@ static void gen_xscvqpdp(DisasContext *ctx)
return;
}
opc = tcg_const_i32(ctx->opcode);
xt = gen_vsr_ptr(xT(ctx->opcode));
xb = gen_vsr_ptr(xB(ctx->opcode));
xt = gen_vsr_ptr(rD(ctx->opcode) + 32);
xb = gen_vsr_ptr(rB(ctx->opcode) + 32);
gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
tcg_temp_free_i32(opc);
tcg_temp_free_ptr(xt);