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target/i386: allow MMX instructions with CR4.OSFXSR=0 

MMX state is saved/restored by FSAVE/FRSTOR so the instructions are
not illegal opcodes even if CR4.OSFXSR=0.  Make sure that validate_vex
takes into account the prefix and only checks HF_OSFXSR_MASK in the
presence of an SSE instruction.

Fixes: 20581aadec ("target/i386: validate VEX prefixes via the instructions' exception classes", 2022-10-18)
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1350
Reported-by: Helge Konetzka (@hejko on gitlab.com)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2022-11-30 15:16:57 +01:00
parent 7c09a7f6ae
commit 38e65936a8
1 changed files with 2 additions and 1 deletions
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3
target/i386/tcg/decode-new.c.inc
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@ -1488,7 +1488,8 @@ static bool validate_vex(DisasContext *s, X86DecodedInsn *decode)
if (!(s->flags & HF_AVX_EN_MASK)) { if (!(s->flags & HF_AVX_EN_MASK)) {
goto illegal; goto illegal;
} }
} else { } else if (e->special != X86_SPECIAL_MMX ||
(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) {
if (!(s->flags & HF_OSFXSR_MASK)) { if (!(s->flags & HF_OSFXSR_MASK)) {
goto illegal; goto illegal;
} }