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target/arm: Change cpreg access permissions to enum 

Create a typedef as well, and use it in ARMCPRegInfo.
This won't be perfect for debugging, but it'll nicely
display the most common cases.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-30 22:49:49 -07:00 committed by Peter Maydell
parent d385a60571
commit 3910733718
2 changed files with 24 additions and 22 deletions
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44
target/arm/cpregs.h
View File

@ -154,31 +154,33 @@ enum {
* described with these bits, then use a laxer set of restrictions, and * described with these bits, then use a laxer set of restrictions, and
* do the more restrictive/complex check inside a helper function. * do the more restrictive/complex check inside a helper function.
*/ */
#define PL3_R 0x80 typedef enum {
#define PL3_W 0x40 PL3_R = 0x80,
#define PL2_R (0x20 | PL3_R) PL3_W = 0x40,
#define PL2_W (0x10 | PL3_W) PL2_R = 0x20 | PL3_R,
#define PL1_R (0x08 | PL2_R) PL2_W = 0x10 | PL3_W,
#define PL1_W (0x04 | PL2_W) PL1_R = 0x08 | PL2_R,
#define PL0_R (0x02 | PL1_R) PL1_W = 0x04 | PL2_W,
#define PL0_W (0x01 | PL1_W) PL0_R = 0x02 | PL1_R,
PL0_W = 0x01 | PL1_W,
/* /*
* For user-mode some registers are accessible to EL0 via a kernel * For user-mode some registers are accessible to EL0 via a kernel
* trap-and-emulate ABI. In this case we define the read permissions * trap-and-emulate ABI. In this case we define the read permissions
* as actually being PL0_R. However some bits of any given register * as actually being PL0_R. However some bits of any given register
* may still be masked. * may still be masked.
*/ */
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
#define PL0U_R PL0_R PL0U_R = PL0_R,
#else #else
#define PL0U_R PL1_R PL0U_R = PL1_R,
#endif #endif
#define PL3_RW (PL3_R | PL3_W) PL3_RW = PL3_R | PL3_W,
#define PL2_RW (PL2_R | PL2_W) PL2_RW = PL2_R | PL2_W,
#define PL1_RW (PL1_R | PL1_W) PL1_RW = PL1_R | PL1_W,
#define PL0_RW (PL0_R | PL0_W) PL0_RW = PL0_R | PL0_W,
} CPAccessRights;
typedef enum CPAccessResult { typedef enum CPAccessResult {
/* Access is permitted */ /* Access is permitted */
@ -262,7 +264,7 @@ struct ARMCPRegInfo {
/* Register type: ARM_CP_* bits/values */ /* Register type: ARM_CP_* bits/values */
int type; int type;
/* Access rights: PL*_[RW] */ /* Access rights: PL*_[RW] */
int access; CPAccessRights access;
/* Security state: ARM_CP_SECSTATE_* bits/values */ /* Security state: ARM_CP_SECSTATE_* bits/values */
int secure; int secure;
/* /*

2
target/arm/helper.c
View File

@ -8711,7 +8711,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
* to encompass the generic architectural permission check. * to encompass the generic architectural permission check.
*/ */
if (r->state != ARM_CP_STATE_AA32) { if (r->state != ARM_CP_STATE_AA32) {
int mask = 0; CPAccessRights mask;
switch (r->opc1) { switch (r->opc1) {
case 0: case 0:
/* min_EL EL1, but some accessible to EL0 via kernel ABI */ /* min_EL EL1, but some accessible to EL0 via kernel ABI */