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serial: Add MemoryRegion parameter to serial_mm_init

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Remove the get_system_memory() call from serial_mm_init, pushing
it back into the callers.  In many cases we already have the
system memory region available.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Richard Henderson 2011-08-11 16:07:16 -07:00 committed by Avi Kivity
parent 2ff0c7c3c2
commit 39186d8ab8
14 changed files with 63 additions and 43 deletions
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8
hw/mips_jazz.c
View File

@ -264,12 +264,12 @@ static void mips_jazz_init(MemoryRegion *address_space,
/* Serial ports */
if (serial_hds[0]) {
serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0],
DEVICE_NATIVE_ENDIAN);
serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16,
serial_hds[0], DEVICE_NATIVE_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1],
DEVICE_NATIVE_ENDIAN);
serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16,
serial_hds[1], DEVICE_NATIVE_ENDIAN);
}
/* Parallel port */

4
hw/mips_malta.c
View File

@ -446,8 +446,8 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
s->display = qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init);
s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr,
DEVICE_NATIVE_ENDIAN);
s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
230400, uart_chr, DEVICE_NATIVE_ENDIAN);
malta_fpga_reset(s);
qemu_register_reset(malta_fpga_reset, s);

8
hw/musicpal.c
View File

@ -1486,12 +1486,12 @@ static void musicpal_init(ram_addr_t ram_size,
pic[MP_TIMER4_IRQ], NULL);
if (serial_hds[0]) {
serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
serial_hds[0], DEVICE_NATIVE_ENDIAN);
serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
1825000, serial_hds[0], DEVICE_NATIVE_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
serial_hds[1], DEVICE_NATIVE_ENDIAN);
serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
1825000, serial_hds[1], DEVICE_NATIVE_ENDIAN);
}
/* Register flash */

6
hw/omap_uart.c
View File

@ -22,6 +22,7 @@
#include "omap.h"
/* We use pc-style serial ports. */
#include "pc.h"
#include "exec-memory.h"
/* UARTs */
struct omap_uart_s {
@ -60,7 +61,8 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
s->base = base;
s->fclk = fclk;
s->irq = irq;
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
s->serial = serial_mm_init(get_system_memory(), base, 2, irq,
omap_clk_getrate(fclk)/16,
chr ?: qemu_chr_new(label, "null", NULL),
DEVICE_NATIVE_ENDIAN);
return s;
@ -176,7 +178,7 @@ struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
{
/* TODO: Should reuse or destroy current s->serial */
s->serial = serial_mm_init(s->base, 2, s->irq,
s->serial = serial_mm_init(get_system_memory(), s->base, 2, s->irq,
omap_clk_getrate(s->fclk) / 16,
chr ?: qemu_chr_new("null", "null", NULL),
DEVICE_NATIVE_ENDIAN);

7
hw/pc.h
View File

@ -15,9 +15,10 @@
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
CharDriverState *chr);
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, enum device_endian);
SerialState *serial_mm_init(MemoryRegion *address_space,
target_phys_addr_t base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, enum device_endian);
static inline bool serial_isa_init(int index, CharDriverState *chr)
{
ISADevice *dev;

6
hw/petalogix_ml605_mmu.c
View File

@ -38,6 +38,7 @@
#include "elf.h"
#include "blockdev.h"
#include "pc.h"
#include "exec-memory.h"
#include "microblaze_pic_cpu.h"
#include "xilinx_axidma.h"
@ -141,6 +142,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev;
CPUState *env;
int kernel_size;
@ -184,8 +186,8 @@ petalogix_ml605_init(ram_addr_t ram_size,
irq[i] = qdev_get_gpio_in(dev, i);
}
serial_mm_init(UART16550_BASEADDR + 0x1000, 2, irq[5], 115200,
serial_hds[0], DEVICE_LITTLE_ENDIAN);
serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2,
irq[5], 115200, serial_hds[0], DEVICE_LITTLE_ENDIAN);
/* 2 timers at irq 2 @ 100 Mhz. */
xilinx_timer_create(TIMER_BASEADDR, irq[2], 2, 100 * 1000000);

20
hw/ppc405_uc.c
View File

@ -2149,12 +2149,14 @@ CPUState *ppc405cr_init (MemoryRegion ram_memories[4],
ppc405_dma_init(env, dma_irqs);
/* Serial ports */
if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
serial_hds[0], DEVICE_BIG_ENDIAN);
serial_mm_init(get_system_memory(), 0xef600300, 0, pic[0],
PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
DEVICE_BIG_ENDIAN);
}
if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
serial_hds[1], DEVICE_BIG_ENDIAN);
serial_mm_init(get_system_memory(), 0xef600400, 0, pic[1],
PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
DEVICE_BIG_ENDIAN);
}
/* IIC controller */
ppc405_i2c_init(0xef600500, pic[2]);
@ -2504,12 +2506,14 @@ CPUState *ppc405ep_init (MemoryRegion ram_memories[2],
ppc405_gpio_init(0xef600700);
/* Serial ports */
if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
serial_hds[0], DEVICE_BIG_ENDIAN);
serial_mm_init(get_system_memory(), 0xef600300, 0, pic[0],
PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
DEVICE_BIG_ENDIAN);
}
if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
serial_hds[1], DEVICE_BIG_ENDIAN);
serial_mm_init(get_system_memory(), 0xef600400, 0, pic[1],
PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
DEVICE_BIG_ENDIAN);
}
/* OCM */
ppc405_ocm_init(env);

11
hw/ppc440.c
View File

@ -20,6 +20,7 @@
#include "ppc405.h"
#include "sysemu.h"
#include "kvm.h"
#include "exec-memory.h"
#define PPC440EP_PCI_CONFIG 0xeec00000
#define PPC440EP_PCI_INTACK 0xeed00000
@ -92,12 +93,14 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
serial_hds[0], DEVICE_BIG_ENDIAN);
serial_mm_init(get_system_memory(), 0xef600300, 0, pic[0],
PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
DEVICE_BIG_ENDIAN);
}
if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
serial_hds[1], DEVICE_BIG_ENDIAN);
serial_mm_init(get_system_memory(), 0xef600400, 0, pic[1],
PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
DEVICE_BIG_ENDIAN);
}
return env;

6
hw/ppce500_mpc8544ds.c
View File

@ -32,6 +32,7 @@
#include "loader.h"
#include "elf.h"
#include "sysbus.h"
#include "exec-memory.h"
#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
#define UIMAGE_LOAD_BASE 0
@ -225,6 +226,7 @@ static void mpc8544ds_init(ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
MemoryRegion *address_space_mem = get_system_memory();
PCIBus *pci_bus;
CPUState *env;
uint64_t elf_entry;
@ -274,13 +276,13 @@ static void mpc8544ds_init(ram_addr_t ram_size,
/* Serial */
if (serial_hds[0]) {
serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE,
0, mpic[12+26], 399193,
serial_hds[0], DEVICE_BIG_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE,
0, mpic[12+26], 399193,
serial_hds[0], DEVICE_BIG_ENDIAN);
}

5
hw/pxa2xx.c
View File

@ -15,6 +15,7 @@
#include "ssi.h"
#include "qemu-char.h"
#include "blockdev.h"
#include "exec-memory.h"
static struct {
target_phys_addr_t io_base;
@ -2115,7 +2116,7 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
for (i = 0; pxa270_serial[i].io_base; i++) {
if (serial_hds[i]) {
serial_mm_init(pxa270_serial[i].io_base, 2,
serial_mm_init(get_system_memory(), pxa270_serial[i].io_base, 2,
qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
14857000 / 16, serial_hds[i],
DEVICE_NATIVE_ENDIAN);
@ -2247,7 +2248,7 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
for (i = 0; pxa255_serial[i].io_base; i++) {
if (serial_hds[i]) {
serial_mm_init(pxa255_serial[i].io_base, 2,
serial_mm_init(get_system_memory(), pxa255_serial[i].io_base, 2,
qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
14745600 / 16, serial_hds[i],
DEVICE_NATIVE_ENDIAN);

10
hw/serial.c
View File

@ -28,7 +28,6 @@
#include "pc.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "exec-memory.h"
//#define DEBUG_SERIAL
@ -855,9 +854,10 @@ static const MemoryRegionOps serial_mm_ops[3] = {
},
};
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, enum device_endian end)
SerialState *serial_mm_init(MemoryRegion *address_space,
target_phys_addr_t base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, enum device_endian end)
{
SerialState *s;
@ -873,7 +873,7 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
memory_region_init_io(&s->io, &serial_mm_ops[end], s,
"serial", 8 << it_shift);
memory_region_add_subregion(get_system_memory(), base, &s->io);
memory_region_add_subregion(address_space, base, &s->io);
serial_update_msl(s);
return s;

4
hw/sm501.c
View File

@ -30,6 +30,7 @@
#include "sysbus.h"
#include "qdev-addr.h"
#include "range.h"
#include "exec-memory.h"
/*
* Status: 2010/05/07
@ -1440,7 +1441,8 @@ void sm501_init(uint32_t base, uint32_t local_mem_bytes, qemu_irq irq,
/* bridge to serial emulation module */
if (chr) {
serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
serial_mm_init(get_system_memory(),
base + MMIO_BASE_OFFSET + SM501_UART0, 2,
NULL, /* TODO : chain irq to IRL */
115200, chr, DEVICE_NATIVE_ENDIAN);
}

5
hw/sun4u.c
View File

@ -38,6 +38,7 @@
#include "loader.h"
#include "elf.h"
#include "blockdev.h"
#include "exec-memory.h"
//#define DEBUG_IRQ
//#define DEBUG_EBUS
@ -770,8 +771,8 @@ static void sun4uv_init(ram_addr_t RAM_size,
i = 0;
if (hwdef->console_serial_base) {
serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
serial_hds[i], DEVICE_BIG_ENDIAN);
serial_mm_init(get_system_memory(), hwdef->console_serial_base, 0,
NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
i++;
}
for(; i < MAX_SERIAL_PORTS; i++) {

6
hw/virtex_ml507.c
View File

@ -34,6 +34,7 @@
#include "loader.h"
#include "elf.h"
#include "qemu-log.h"
#include "exec-memory.h"
#include "ppc.h"
#include "ppc4xx.h"
@ -191,6 +192,7 @@ static void virtex_init(ram_addr_t ram_size,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev;
CPUState *env;
target_phys_addr_t ram_base = 0;
@ -226,8 +228,8 @@ static void virtex_init(ram_addr_t ram_size,
irq[i] = qdev_get_gpio_in(dev, i);
}
serial_mm_init(0x83e01003ULL, 2, irq[9], 115200, serial_hds[0],
DEVICE_LITTLE_ENDIAN);
serial_mm_init(address_space_mem, 0x83e01003ULL, 2, irq[9], 115200,
serial_hds[0], DEVICE_LITTLE_ENDIAN);
/* 2 timers at irq 2 @ 62 Mhz. */
xilinx_timer_create(0x83c00000, irq[3], 2, 62 * 1000000);