vfio-pci: VGA quirk update
Turns out all the suspicions for AMD devices were correct, everywhere we read a BAR address that the address matches the config space offset, there's full access to PCI config space. Attempt to generalize some helpers to allow quirks to easily be added for mirrors and windows. Also fill in complete config space for AMD. Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
This commit is contained in:
Alex Williamson
parent
c3cb8e7780
commit
39360f0b91
659
hw/misc/vfio.c
659
hw/misc/vfio.c
@ -59,8 +59,23 @@ typedef struct VFIOQuirk {
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MemoryRegion mem;
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struct VFIODevice *vdev;
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QLIST_ENTRY(VFIOQuirk) next;
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uint32_t data;
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uint32_t data2;
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struct {
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uint32_t base_offset:TARGET_PAGE_BITS;
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uint32_t address_offset:TARGET_PAGE_BITS;
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uint32_t address_size:3;
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uint32_t bar:3;
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uint32_t address_match;
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uint32_t address_mask;
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uint32_t address_val:TARGET_PAGE_BITS;
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uint32_t data_offset:TARGET_PAGE_BITS;
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uint32_t data_size:3;
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uint8_t flags;
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uint8_t read_flags;
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uint8_t write_flags;
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} data;
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} VFIOQuirk;
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typedef struct VFIOBAR {
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@ -72,6 +87,8 @@ typedef struct VFIOBAR {
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size_t size;
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uint32_t flags; /* VFIO region flags (rd/wr/mmap) */
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uint8_t nr; /* cache the BAR number for debug */
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bool ioport;
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bool mem64;
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QLIST_HEAD(, VFIOQuirk) quirks;
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} VFIOBAR;
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@ -1097,30 +1114,188 @@ static const MemoryRegionOps vfio_vga_ops = {
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* Device specific quirks
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*/
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/* Is range1 fully contained within range2? */
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static bool vfio_range_contained(uint64_t first1, uint64_t len1,
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uint64_t first2, uint64_t len2) {
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return (first1 >= first2 && first1 + len1 <= first2 + len2);
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}
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static bool vfio_flags_enabled(uint8_t flags, uint8_t mask)
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{
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return (mask && (flags & mask) == mask);
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}
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static uint64_t vfio_generic_window_quirk_read(void *opaque,
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hwaddr addr, unsigned size)
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{
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VFIOQuirk *quirk = opaque;
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VFIODevice *vdev = quirk->vdev;
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uint64_t data;
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if (vfio_flags_enabled(quirk->data.flags, quirk->data.read_flags) &&
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ranges_overlap(addr, size,
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quirk->data.data_offset, quirk->data.data_size)) {
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hwaddr offset = addr - quirk->data.data_offset;
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if (!vfio_range_contained(addr, size, quirk->data.data_offset,
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quirk->data.data_size)) {
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hw_error("%s: window data read not fully contained: %s\n",
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__func__, memory_region_name(&quirk->mem));
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}
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data = vfio_pci_read_config(&vdev->pdev,
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quirk->data.address_val + offset, size);
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DPRINTF("%s read(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx", %d) = 0x%"
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PRIx64"\n", memory_region_name(&quirk->mem), vdev->host.domain,
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vdev->host.bus, vdev->host.slot, vdev->host.function,
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quirk->data.bar, addr, size, data);
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} else {
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data = vfio_bar_read(&vdev->bars[quirk->data.bar],
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addr + quirk->data.base_offset, size);
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}
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return data;
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}
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static void vfio_generic_window_quirk_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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VFIOQuirk *quirk = opaque;
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VFIODevice *vdev = quirk->vdev;
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if (ranges_overlap(addr, size,
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quirk->data.address_offset, quirk->data.address_size)) {
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if (addr != quirk->data.address_offset) {
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hw_error("%s: offset write into address window: %s\n",
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__func__, memory_region_name(&quirk->mem));
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}
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if ((data & ~quirk->data.address_mask) == quirk->data.address_match) {
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quirk->data.flags |= quirk->data.write_flags |
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quirk->data.read_flags;
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quirk->data.address_val = data & quirk->data.address_mask;
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} else {
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quirk->data.flags &= ~(quirk->data.write_flags |
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quirk->data.read_flags);
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}
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}
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if (vfio_flags_enabled(quirk->data.flags, quirk->data.write_flags) &&
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ranges_overlap(addr, size,
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quirk->data.data_offset, quirk->data.data_size)) {
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hwaddr offset = addr - quirk->data.data_offset;
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if (!vfio_range_contained(addr, size, quirk->data.data_offset,
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quirk->data.data_size)) {
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hw_error("%s: window data write not fully contained: %s\n",
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__func__, memory_region_name(&quirk->mem));
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}
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vfio_pci_write_config(&vdev->pdev,
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quirk->data.address_val + offset, data, size);
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DPRINTF("%s write(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx", 0x%"
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PRIx64", %d)\n", memory_region_name(&quirk->mem),
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vdev->host.domain, vdev->host.bus, vdev->host.slot,
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vdev->host.function, quirk->data.bar, addr, data, size);
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return;
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}
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vfio_bar_write(&vdev->bars[quirk->data.bar],
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addr + quirk->data.base_offset, data, size);
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}
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static const MemoryRegionOps vfio_generic_window_quirk = {
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.read = vfio_generic_window_quirk_read,
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.write = vfio_generic_window_quirk_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t vfio_generic_quirk_read(void *opaque,
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hwaddr addr, unsigned size)
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{
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VFIOQuirk *quirk = opaque;
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VFIODevice *vdev = quirk->vdev;
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hwaddr base = quirk->data.address_match & TARGET_PAGE_MASK;
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hwaddr offset = quirk->data.address_match & ~TARGET_PAGE_MASK;
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uint64_t data;
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if (vfio_flags_enabled(quirk->data.flags, quirk->data.read_flags) &&
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ranges_overlap(addr, size, offset, quirk->data.address_mask + 1)) {
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if (!vfio_range_contained(addr, size, offset,
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quirk->data.address_mask + 1)) {
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hw_error("%s: read not fully contained: %s\n",
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__func__, memory_region_name(&quirk->mem));
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}
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data = vfio_pci_read_config(&vdev->pdev, addr - offset, size);
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DPRINTF("%s read(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx", %d) = 0x%"
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PRIx64"\n", memory_region_name(&quirk->mem), vdev->host.domain,
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vdev->host.bus, vdev->host.slot, vdev->host.function,
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quirk->data.bar, addr + base, size, data);
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} else {
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data = vfio_bar_read(&vdev->bars[quirk->data.bar], addr + base, size);
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}
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return data;
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}
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static void vfio_generic_quirk_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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VFIOQuirk *quirk = opaque;
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VFIODevice *vdev = quirk->vdev;
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hwaddr base = quirk->data.address_match & TARGET_PAGE_MASK;
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hwaddr offset = quirk->data.address_match & ~TARGET_PAGE_MASK;
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if (vfio_flags_enabled(quirk->data.flags, quirk->data.write_flags) &&
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ranges_overlap(addr, size, offset, quirk->data.address_mask + 1)) {
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if (!vfio_range_contained(addr, size, offset,
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quirk->data.address_mask + 1)) {
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hw_error("%s: write not fully contained: %s\n",
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__func__, memory_region_name(&quirk->mem));
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}
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vfio_pci_write_config(&vdev->pdev, addr - offset, data, size);
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DPRINTF("%s write(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx", 0x%"
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PRIx64", %d)\n", memory_region_name(&quirk->mem),
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vdev->host.domain, vdev->host.bus, vdev->host.slot,
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vdev->host.function, quirk->data.bar, addr + base, data, size);
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} else {
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vfio_bar_write(&vdev->bars[quirk->data.bar], addr + base, data, size);
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}
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}
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static const MemoryRegionOps vfio_generic_quirk = {
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.read = vfio_generic_quirk_read,
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.write = vfio_generic_quirk_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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#define PCI_VENDOR_ID_ATI 0x1002
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/*
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* Device 1002:68f9 (Advanced Micro Devices [AMD] nee ATI Cedar PRO [Radeon
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* HD 5450/6350]) reports the upper byte of the physical address of the
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* I/O port BAR4 through VGA register 0x3c3. The BAR is 256 bytes, so the
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* lower byte is known to be zero. Probing for this quirk reads 0xff from
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* port 0x3c3 on some devices so we store the physical address and replace
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* reads with the virtual address any time it matches. XXX Research when
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* to enable quirk.
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* Radeon HD cards (HD5450 & HD7850) report the upper byte of the I/O port BAR
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* through VGA register 0x3c3. On newer cards, the I/O port BAR is always
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* BAR4 (older cards like the X550 used BAR1, but we don't care to support
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* those). Note that on bare metal, a read of 0x3c3 doesn't always return the
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* I/O port BAR address. Originally this was coded to return the virtual BAR
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* address only if the physical register read returns the actual BAR address,
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* but users have reported greater success if we return the virtual address
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* unconditionally.
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*/
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static uint64_t vfio_ati_3c3_quirk_read(void *opaque,
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hwaddr addr, unsigned size)
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{
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VFIOQuirk *quirk = opaque;
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VFIODevice *vdev = quirk->vdev;
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PCIDevice *pdev = &vdev->pdev;
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uint64_t data = vfio_vga_read(&vdev->vga.region[QEMU_PCI_VGA_IO_HI],
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addr + 0x3, size);
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if (data == quirk->data) {
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data = pci_get_byte(pdev->config + PCI_BASE_ADDRESS_4 + 1);
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DPRINTF("%s(0x3c3, 1) = 0x%"PRIx64"\n", __func__, data);
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}
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uint64_t data = vfio_pci_read_config(&vdev->pdev,
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PCI_BASE_ADDRESS_0 + (4 * 4) + 1,
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size);
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DPRINTF("%s(0x3c3, 1) = 0x%"PRIx64"\n", __func__, data);
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return data;
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}
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@ -1133,215 +1308,121 @@ static const MemoryRegionOps vfio_ati_3c3_quirk = {
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static void vfio_vga_probe_ati_3c3_quirk(VFIODevice *vdev)
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{
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PCIDevice *pdev = &vdev->pdev;
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off_t physoffset = vdev->config_offset + PCI_BASE_ADDRESS_4;
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uint32_t physbar;
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VFIOQuirk *quirk;
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if (pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_ATI ||
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vdev->bars[4].size < 256) {
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if (pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_ATI) {
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return;
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}
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/* Get I/O port BAR physical address */
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if (pread(vdev->fd, &physbar, 4, physoffset) != 4) {
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error_report("vfio: probe failed for ATI/AMD 0x3c3 quirk on device "
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"%04x:%02x:%02x.%x", vdev->host.domain,
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vdev->host.bus, vdev->host.slot, vdev->host.function);
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/*
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* As long as the BAR is >= 256 bytes it will be aligned such that the
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* lower byte is always zero. Filter out anything else, if it exists.
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*/
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if (!vdev->bars[4].ioport || vdev->bars[4].size < 256) {
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return;
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}
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quirk = g_malloc0(sizeof(*quirk));
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quirk->vdev = vdev;
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quirk->data = (physbar >> 8) & 0xff;
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memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_ati_3c3_quirk, quirk,
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"vfio-ati-3c3-quirk", 1);
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memory_region_add_subregion(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem, 3,
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&quirk->mem);
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memory_region_add_subregion(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem,
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3 /* offset 3 bytes from 0x3c0 */, &quirk->mem);
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QLIST_INSERT_HEAD(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].quirks,
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quirk, next);
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DPRINTF("Enabled ATI/AMD quirk 0x3c3 for device %04x:%02x:%02x.%x\n",
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DPRINTF("Enabled ATI/AMD quirk 0x3c3 BAR4for device %04x:%02x:%02x.%x\n",
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vdev->host.domain, vdev->host.bus, vdev->host.slot,
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vdev->host.function);
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}
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/*
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* Device 1002:68f9 (Advanced Micro Devices [AMD] nee ATI Cedar PRO [Radeon
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* HD 5450/6350]) reports the physical address of MMIO BAR0 through a
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* write/read operation on I/O port BAR4. When uint32_t 0x4010 is written
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* to offset 0x0, the subsequent read from offset 0x4 returns the contents
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* of BAR0. Test for this quirk on all ATI/AMD devices. XXX - Note that
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* 0x10 is the offset of BAR0 in config sapce, is this a window to all of
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* config space?
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* Newer ATI/AMD devices, including HD5450 and HD7850, have a window to PCI
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* config space through MMIO BAR2 at offset 0x4000. Nothing seems to access
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* the MMIO space directly, but a window to this space is provided through
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* I/O port BAR4. Offset 0x0 is the address register and offset 0x4 is the
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* data register. When the address is programmed to a range of 0x4000-0x4fff
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* PCI configuration space is available. Experimentation seems to indicate
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* that only read-only access is provided, but we drop writes when the window
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* is enabled to config space nonetheless.
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*/
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static uint64_t vfio_ati_4010_quirk_read(void *opaque,
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hwaddr addr, unsigned size)
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{
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VFIOQuirk *quirk = opaque;
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VFIODevice *vdev = quirk->vdev;
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PCIDevice *pdev = &vdev->pdev;
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uint64_t data = vfio_bar_read(&vdev->bars[4], addr, size);
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if (addr == 4 && size == 4 && quirk->data) {
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data = pci_get_long(pdev->config + PCI_BASE_ADDRESS_0);
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DPRINTF("%s(BAR4+0x4) = 0x%"PRIx64"\n", __func__, data);
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}
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quirk->data = 0;
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return data;
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}
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static void vfio_ati_4010_quirk_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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VFIOQuirk *quirk = opaque;
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VFIODevice *vdev = quirk->vdev;
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vfio_bar_write(&vdev->bars[4], addr, data, size);
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quirk->data = (addr == 0 && size == 4 && data == 0x4010) ? 1 : 0;
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}
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static const MemoryRegionOps vfio_ati_4010_quirk = {
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.read = vfio_ati_4010_quirk_read,
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.write = vfio_ati_4010_quirk_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void vfio_probe_ati_4010_quirk(VFIODevice *vdev, int nr)
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static void vfio_probe_ati_bar4_window_quirk(VFIODevice *vdev, int nr)
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{
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PCIDevice *pdev = &vdev->pdev;
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off_t physoffset = vdev->config_offset + PCI_BASE_ADDRESS_0;
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uint32_t physbar0;
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uint64_t data;
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VFIOQuirk *quirk;
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if (!vdev->has_vga || nr != 4 || !vdev->bars[0].size ||
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if (!vdev->has_vga || nr != 4 ||
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pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_ATI) {
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return;
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}
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/* Get I/O port BAR physical address */
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if (pread(vdev->fd, &physbar0, 4, physoffset) != 4) {
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error_report("vfio: probe failed for ATI/AMD 0x4010 quirk on device "
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"%04x:%02x:%02x.%x", vdev->host.domain,
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vdev->host.bus, vdev->host.slot, vdev->host.function);
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return;
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}
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/* Write 0x4010 to I/O port BAR offset 0 */
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vfio_bar_write(&vdev->bars[4], 0, 0x4010, 4);
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/* Read back result */
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data = vfio_bar_read(&vdev->bars[4], 4, 4);
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/* If the register matches the physical address of BAR0, we need a quirk */
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if (data != physbar0) {
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return;
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}
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quirk = g_malloc0(sizeof(*quirk));
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quirk->vdev = vdev;
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quirk->data.address_size = 4;
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quirk->data.data_offset = 4;
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quirk->data.data_size = 4;
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quirk->data.address_match = 0x4000;
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quirk->data.address_mask = PCIE_CONFIG_SPACE_SIZE - 1;
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quirk->data.bar = nr;
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quirk->data.read_flags = quirk->data.write_flags = 1;
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memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_ati_4010_quirk, quirk,
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"vfio-ati-4010-quirk", 8);
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memory_region_add_subregion_overlap(&vdev->bars[nr].mem, 0, &quirk->mem, 1);
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memory_region_init_io(&quirk->mem, OBJECT(vdev),
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&vfio_generic_window_quirk, quirk,
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"vfio-ati-bar4-window-quirk", 8);
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memory_region_add_subregion_overlap(&vdev->bars[nr].mem,
|
||||
quirk->data.base_offset, &quirk->mem, 1);
|
||||
|
||||
QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);
|
||||
|
||||
DPRINTF("Enabled ATI/AMD quirk 0x4010 for device %04x:%02x:%02x.%x\n",
|
||||
DPRINTF("Enabled ATI/AMD BAR4 window quirk for device %04x:%02x:%02x.%x\n",
|
||||
vdev->host.domain, vdev->host.bus, vdev->host.slot,
|
||||
vdev->host.function);
|
||||
}
|
||||
|
||||
/*
|
||||
* Device 1002:5b63 (Advanced Micro Devices [AMD] nee ATI RV370 [Radeon X550])
|
||||
* retrieves the upper half of the MMIO BAR0 physical address by writing
|
||||
* 0xf10 to I/O port BAR1 offset 0 and reading the result from offset 6.
|
||||
* XXX - 0x10 is the offset of BAR0 in PCI config space, this could provide
|
||||
* full access to config space. Config space is little endian, so the data
|
||||
* register probably starts at 0x4.
|
||||
* Trap the BAR2 MMIO window to config space as well.
|
||||
*/
|
||||
static uint64_t vfio_ati_f10_quirk_read(void *opaque,
|
||||
hwaddr addr, unsigned size)
|
||||
{
|
||||
VFIOQuirk *quirk = opaque;
|
||||
VFIODevice *vdev = quirk->vdev;
|
||||
PCIDevice *pdev = &vdev->pdev;
|
||||
uint64_t data = vfio_bar_read(&vdev->bars[1], addr, size);
|
||||
|
||||
if (addr == 6 && size == 2 && quirk->data) {
|
||||
data = pci_get_word(pdev->config + PCI_BASE_ADDRESS_0 + 2);
|
||||
DPRINTF("%s(BAR1+0x6) = 0x%"PRIx64"\n", __func__, data);
|
||||
}
|
||||
|
||||
quirk->data = 0;
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
static void vfio_ati_f10_quirk_write(void *opaque, hwaddr addr,
|
||||
uint64_t data, unsigned size)
|
||||
{
|
||||
VFIOQuirk *quirk = opaque;
|
||||
VFIODevice *vdev = quirk->vdev;
|
||||
|
||||
vfio_bar_write(&vdev->bars[1], addr, data, size);
|
||||
|
||||
quirk->data = (addr == 0 && size == 4 && data == 0xf10) ? 1 : 0;
|
||||
}
|
||||
|
||||
static const MemoryRegionOps vfio_ati_f10_quirk = {
|
||||
.read = vfio_ati_f10_quirk_read,
|
||||
.write = vfio_ati_f10_quirk_write,
|
||||
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||
};
|
||||
|
||||
static void vfio_probe_ati_f10_quirk(VFIODevice *vdev, int nr)
|
||||
static void vfio_probe_ati_bar2_4000_quirk(VFIODevice *vdev, int nr)
|
||||
{
|
||||
PCIDevice *pdev = &vdev->pdev;
|
||||
off_t physoffset = vdev->config_offset + PCI_BASE_ADDRESS_0;
|
||||
uint32_t physbar0;
|
||||
uint64_t data;
|
||||
VFIOQuirk *quirk;
|
||||
|
||||
if (!vdev->has_vga || nr != 1 || !vdev->bars[0].size ||
|
||||
/* Only enable on newer devices where BAR2 is 64bit */
|
||||
if (!vdev->has_vga || nr != 2 || !vdev->bars[2].mem64 ||
|
||||
pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_ATI) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* Get I/O port BAR physical address */
|
||||
if (pread(vdev->fd, &physbar0, 4, physoffset) != 4) {
|
||||
error_report("vfio: probe failed for ATI/AMD 0xf10 quirk on device "
|
||||
"%04x:%02x:%02x.%x", vdev->host.domain,
|
||||
vdev->host.bus, vdev->host.slot, vdev->host.function);
|
||||
return;
|
||||
}
|
||||
|
||||
vfio_bar_write(&vdev->bars[1], 0, 0xf10, 4);
|
||||
data = vfio_bar_read(&vdev->bars[1], 0x6, 2);
|
||||
|
||||
/* If the register matches the physical address of BAR0, we need a quirk */
|
||||
if (data != (le32_to_cpu(physbar0) >> 16)) {
|
||||
return;
|
||||
}
|
||||
|
||||
quirk = g_malloc0(sizeof(*quirk));
|
||||
quirk->vdev = vdev;
|
||||
quirk->data.flags = quirk->data.read_flags = quirk->data.write_flags = 1;
|
||||
quirk->data.address_match = 0x4000;
|
||||
quirk->data.address_mask = PCIE_CONFIG_SPACE_SIZE - 1;
|
||||
quirk->data.bar = nr;
|
||||
|
||||
memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_ati_f10_quirk, quirk,
|
||||
"vfio-ati-f10-quirk", 8);
|
||||
memory_region_add_subregion_overlap(&vdev->bars[nr].mem, 0, &quirk->mem, 1);
|
||||
memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_generic_quirk, quirk,
|
||||
"vfio-ati-bar2-4000-quirk",
|
||||
TARGET_PAGE_ALIGN(quirk->data.address_mask + 1));
|
||||
memory_region_add_subregion_overlap(&vdev->bars[nr].mem,
|
||||
quirk->data.address_match & TARGET_PAGE_MASK,
|
||||
&quirk->mem, 1);
|
||||
|
||||
QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);
|
||||
|
||||
DPRINTF("Enabled ATI/AMD quirk 0xf10 for device %04x:%02x:%02x.%x\n",
|
||||
DPRINTF("Enabled ATI/AMD BAR2 0x4000 quirk for device %04x:%02x:%02x.%x\n",
|
||||
vdev->host.domain, vdev->host.bus, vdev->host.slot,
|
||||
vdev->host.function);
|
||||
}
|
||||
|
||||
/*
|
||||
* Older ATI/AMD cards like the X550 have a similar window to that above.
|
||||
* I/O port BAR1 provides a window to a mirror of PCI config space located
|
||||
* in BAR2 at offset 0xf00. We don't care to support such older cards, but
|
||||
* note it for future reference.
|
||||
*/
|
||||
|
||||
#define PCI_VENDOR_ID_NVIDIA 0x10de
|
||||
|
||||
/*
|
||||
@ -1360,7 +1441,7 @@ static void vfio_probe_ati_f10_quirk(VFIODevice *vdev, int nr)
|
||||
* that use the I/O port BAR5 window but it doesn't hurt to leave it.
|
||||
*/
|
||||
enum {
|
||||
NV_3D0_NONE,
|
||||
NV_3D0_NONE = 0,
|
||||
NV_3D0_SELECT,
|
||||
NV_3D0_WINDOW,
|
||||
NV_3D0_READ,
|
||||
@ -1374,14 +1455,14 @@ static uint64_t vfio_nvidia_3d0_quirk_read(void *opaque,
|
||||
VFIODevice *vdev = quirk->vdev;
|
||||
PCIDevice *pdev = &vdev->pdev;
|
||||
uint64_t data = vfio_vga_read(&vdev->vga.region[QEMU_PCI_VGA_IO_HI],
|
||||
addr + 0x10, size);
|
||||
addr + quirk->data.base_offset, size);
|
||||
|
||||
if (quirk->data == NV_3D0_READ && addr == 0) {
|
||||
data = vfio_pci_read_config(pdev, quirk->data2, size);
|
||||
if (quirk->data.flags == NV_3D0_READ && addr == quirk->data.data_offset) {
|
||||
data = vfio_pci_read_config(pdev, quirk->data.address_val, size);
|
||||
DPRINTF("%s(0x3d0, %d) = 0x%"PRIx64"\n", __func__, size, data);
|
||||
}
|
||||
|
||||
quirk->data = NV_3D0_NONE;
|
||||
quirk->data.flags = NV_3D0_NONE;
|
||||
|
||||
return data;
|
||||
}
|
||||
@ -1393,43 +1474,42 @@ static void vfio_nvidia_3d0_quirk_write(void *opaque, hwaddr addr,
|
||||
VFIODevice *vdev = quirk->vdev;
|
||||
PCIDevice *pdev = &vdev->pdev;
|
||||
|
||||
switch (quirk->data) {
|
||||
switch (quirk->data.flags) {
|
||||
case NV_3D0_NONE:
|
||||
if (addr == 4 && data == 0x338) {
|
||||
quirk->data = NV_3D0_SELECT;
|
||||
if (addr == quirk->data.address_offset && data == 0x338) {
|
||||
quirk->data.flags = NV_3D0_SELECT;
|
||||
}
|
||||
break;
|
||||
case NV_3D0_SELECT:
|
||||
quirk->data = NV_3D0_NONE;
|
||||
if (addr == 0 && (data & ~0xff) == 0x1800) {
|
||||
quirk->data = NV_3D0_WINDOW;
|
||||
quirk->data2 = data & 0xff;
|
||||
quirk->data.flags = NV_3D0_NONE;
|
||||
if (addr == quirk->data.data_offset &&
|
||||
(data & ~quirk->data.address_mask) == quirk->data.address_match) {
|
||||
quirk->data.flags = NV_3D0_WINDOW;
|
||||
quirk->data.address_val = data & quirk->data.address_mask;
|
||||
}
|
||||
break;
|
||||
case NV_3D0_WINDOW:
|
||||
quirk->data = NV_3D0_NONE;
|
||||
if (addr == 4) {
|
||||
quirk->data.flags = NV_3D0_NONE;
|
||||
if (addr == quirk->data.address_offset) {
|
||||
if (data == 0x538) {
|
||||
quirk->data = NV_3D0_READ;
|
||||
quirk->data.flags = NV_3D0_READ;
|
||||
} else if (data == 0x738) {
|
||||
quirk->data = NV_3D0_WRITE;
|
||||
quirk->data.flags = NV_3D0_WRITE;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case NV_3D0_WRITE:
|
||||
quirk->data = NV_3D0_NONE;
|
||||
if (addr == 0) {
|
||||
vfio_pci_write_config(pdev, quirk->data2, data, size);
|
||||
quirk->data.flags = NV_3D0_NONE;
|
||||
if (addr == quirk->data.data_offset) {
|
||||
vfio_pci_write_config(pdev, quirk->data.address_val, data, size);
|
||||
DPRINTF("%s(0x3d0, 0x%"PRIx64", %d)\n", __func__, data, size);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
quirk->data = NV_3D0_NONE;
|
||||
}
|
||||
|
||||
vfio_vga_write(&vdev->vga.region[QEMU_PCI_VGA_IO_HI],
|
||||
addr + 0x10, data, size);
|
||||
addr + quirk->data.base_offset, data, size);
|
||||
}
|
||||
|
||||
static const MemoryRegionOps vfio_nvidia_3d0_quirk = {
|
||||
@ -1450,11 +1530,18 @@ static void vfio_vga_probe_nvidia_3d0_quirk(VFIODevice *vdev)
|
||||
|
||||
quirk = g_malloc0(sizeof(*quirk));
|
||||
quirk->vdev = vdev;
|
||||
quirk->data.base_offset = 0x10;
|
||||
quirk->data.address_offset = 4;
|
||||
quirk->data.address_size = 2;
|
||||
quirk->data.address_match = 0x1800;
|
||||
quirk->data.address_mask = PCI_CONFIG_SPACE_SIZE - 1;
|
||||
quirk->data.data_offset = 0;
|
||||
quirk->data.data_size = 4;
|
||||
|
||||
memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_nvidia_3d0_quirk, quirk,
|
||||
"vfio-nvidia-3d0-quirk", 6);
|
||||
memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_nvidia_3d0_quirk,
|
||||
quirk, "vfio-nvidia-3d0-quirk", 6);
|
||||
memory_region_add_subregion(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem,
|
||||
0x10, &quirk->mem);
|
||||
quirk->data.base_offset, &quirk->mem);
|
||||
|
||||
QLIST_INSERT_HEAD(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].quirks,
|
||||
quirk, next);
|
||||
@ -1478,76 +1565,46 @@ enum {
|
||||
NV_BAR5_VALID = 0x7,
|
||||
};
|
||||
|
||||
static uint64_t vfio_nvidia_bar5_window_quirk_read(void *opaque,
|
||||
hwaddr addr, unsigned size)
|
||||
{
|
||||
VFIOQuirk *quirk = opaque;
|
||||
VFIODevice *vdev = quirk->vdev;
|
||||
uint64_t data = vfio_bar_read(&vdev->bars[5], addr, size);
|
||||
|
||||
if (addr == 0xc && quirk->data == NV_BAR5_VALID) {
|
||||
data = vfio_pci_read_config(&vdev->pdev, quirk->data2, size);
|
||||
DPRINTF("%s(%04x:%02x:%02x.%x:BAR5+0x%"HWADDR_PRIx", %d) = 0x%"
|
||||
PRIx64"\n", __func__, vdev->host.domain, vdev->host.bus,
|
||||
vdev->host.slot, vdev->host.function, addr, size, data);
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
static void vfio_nvidia_bar5_window_quirk_write(void *opaque, hwaddr addr,
|
||||
uint64_t data, unsigned size)
|
||||
{
|
||||
VFIOQuirk *quirk = opaque;
|
||||
VFIODevice *vdev = quirk->vdev;
|
||||
|
||||
/*
|
||||
* Use quirk->data to track enables and quirk->data2 for the offset
|
||||
*/
|
||||
switch (addr) {
|
||||
case 0x0:
|
||||
if (data & 0x1) {
|
||||
quirk->data |= NV_BAR5_MASTER;
|
||||
quirk->data.flags |= NV_BAR5_MASTER;
|
||||
} else {
|
||||
quirk->data &= ~NV_BAR5_MASTER;
|
||||
quirk->data.flags &= ~NV_BAR5_MASTER;
|
||||
}
|
||||
break;
|
||||
case 0x4:
|
||||
if (data & 0x1) {
|
||||
quirk->data |= NV_BAR5_ENABLE;
|
||||
quirk->data.flags |= NV_BAR5_ENABLE;
|
||||
} else {
|
||||
quirk->data &= ~NV_BAR5_ENABLE;
|
||||
quirk->data.flags &= ~NV_BAR5_ENABLE;
|
||||
}
|
||||
break;
|
||||
case 0x8:
|
||||
if (quirk->data & NV_BAR5_MASTER) {
|
||||
if (quirk->data.flags & NV_BAR5_MASTER) {
|
||||
if ((data & ~0xfff) == 0x88000) {
|
||||
quirk->data |= NV_BAR5_ADDRESS;
|
||||
quirk->data2 = data & 0xfff;
|
||||
quirk->data.flags |= NV_BAR5_ADDRESS;
|
||||
quirk->data.address_val = data & 0xfff;
|
||||
} else if ((data & ~0xff) == 0x1800) {
|
||||
quirk->data |= NV_BAR5_ADDRESS;
|
||||
quirk->data2 = data & 0xff;
|
||||
quirk->data.flags |= NV_BAR5_ADDRESS;
|
||||
quirk->data.address_val = data & 0xff;
|
||||
} else {
|
||||
quirk->data &= ~NV_BAR5_ADDRESS;
|
||||
quirk->data.flags &= ~NV_BAR5_ADDRESS;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0xc:
|
||||
if (quirk->data == NV_BAR5_VALID) {
|
||||
vfio_pci_write_config(&vdev->pdev, quirk->data2, data, size);
|
||||
DPRINTF("%s(%04x:%02x:%02x.%x:BAR5+0x%"HWADDR_PRIx", 0x%"
|
||||
PRIx64", %d)\n", __func__, vdev->host.domain,
|
||||
vdev->host.bus, vdev->host.slot, vdev->host.function,
|
||||
addr, data, size);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
vfio_bar_write(&vdev->bars[5], addr, data, size);
|
||||
vfio_generic_window_quirk_write(opaque, addr, data, size);
|
||||
}
|
||||
|
||||
static const MemoryRegionOps vfio_nvidia_bar5_window_quirk = {
|
||||
.read = vfio_nvidia_bar5_window_quirk_read,
|
||||
.read = vfio_generic_window_quirk_read,
|
||||
.write = vfio_nvidia_bar5_window_quirk_write,
|
||||
.valid.min_access_size = 4,
|
||||
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||
@ -1565,8 +1622,15 @@ static void vfio_probe_nvidia_bar5_window_quirk(VFIODevice *vdev, int nr)
|
||||
|
||||
quirk = g_malloc0(sizeof(*quirk));
|
||||
quirk->vdev = vdev;
|
||||
quirk->data.read_flags = quirk->data.write_flags = NV_BAR5_VALID;
|
||||
quirk->data.address_offset = 0x8;
|
||||
quirk->data.address_size = 0; /* actually 4, but avoids generic code */
|
||||
quirk->data.data_offset = 0xc;
|
||||
quirk->data.data_size = 4;
|
||||
quirk->data.bar = nr;
|
||||
|
||||
memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_nvidia_bar5_window_quirk, quirk,
|
||||
memory_region_init_io(&quirk->mem, OBJECT(vdev),
|
||||
&vfio_nvidia_bar5_window_quirk, quirk,
|
||||
"vfio-nvidia-bar5-window-quirk", 16);
|
||||
memory_region_add_subregion_overlap(&vdev->bars[nr].mem, 0, &quirk->mem, 1);
|
||||
|
||||
@ -1586,51 +1650,6 @@ static void vfio_probe_nvidia_bar5_window_quirk(VFIODevice *vdev, int nr)
|
||||
*
|
||||
* Here's offset 0x88000...
|
||||
*/
|
||||
static uint64_t vfio_nvidia_bar0_88000_quirk_read(void *opaque,
|
||||
hwaddr addr, unsigned size)
|
||||
{
|
||||
VFIOQuirk *quirk = opaque;
|
||||
VFIODevice *vdev = quirk->vdev;
|
||||
hwaddr base = 0x88000 & TARGET_PAGE_MASK;
|
||||
hwaddr offset = 0x88000 & ~TARGET_PAGE_MASK;
|
||||
uint64_t data = vfio_bar_read(&vdev->bars[0], addr + base, size);
|
||||
|
||||
if (ranges_overlap(addr, size, offset, PCI_CONFIG_SPACE_SIZE)) {
|
||||
data = vfio_pci_read_config(&vdev->pdev, addr - offset, size);
|
||||
|
||||
DPRINTF("%s(%04x:%02x:%02x.%x:BAR0+0x%"HWADDR_PRIx", %d) = 0x%"
|
||||
PRIx64"\n", __func__, vdev->host.domain, vdev->host.bus,
|
||||
vdev->host.slot, vdev->host.function, addr + base, size, data);
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
static void vfio_nvidia_bar0_88000_quirk_write(void *opaque, hwaddr addr,
|
||||
uint64_t data, unsigned size)
|
||||
{
|
||||
VFIOQuirk *quirk = opaque;
|
||||
VFIODevice *vdev = quirk->vdev;
|
||||
hwaddr base = 0x88000 & TARGET_PAGE_MASK;
|
||||
hwaddr offset = 0x88000 & ~TARGET_PAGE_MASK;
|
||||
|
||||
if (ranges_overlap(addr, size, offset, PCI_CONFIG_SPACE_SIZE)) {
|
||||
vfio_pci_write_config(&vdev->pdev, addr - offset, data, size);
|
||||
|
||||
DPRINTF("%s(%04x:%02x:%02x.%x:BAR0+0x%"HWADDR_PRIx", 0x%"
|
||||
PRIx64", %d)\n", __func__, vdev->host.domain, vdev->host.bus,
|
||||
vdev->host.slot, vdev->host.function, addr + base, data, size);
|
||||
} else {
|
||||
vfio_bar_write(&vdev->bars[0], addr + base, data, size);
|
||||
}
|
||||
}
|
||||
|
||||
static const MemoryRegionOps vfio_nvidia_bar0_88000_quirk = {
|
||||
.read = vfio_nvidia_bar0_88000_quirk_read,
|
||||
.write = vfio_nvidia_bar0_88000_quirk_write,
|
||||
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||
};
|
||||
|
||||
static void vfio_probe_nvidia_bar0_88000_quirk(VFIODevice *vdev, int nr)
|
||||
{
|
||||
PCIDevice *pdev = &vdev->pdev;
|
||||
@ -1643,13 +1662,17 @@ static void vfio_probe_nvidia_bar0_88000_quirk(VFIODevice *vdev, int nr)
|
||||
|
||||
quirk = g_malloc0(sizeof(*quirk));
|
||||
quirk->vdev = vdev;
|
||||
quirk->data.flags = quirk->data.read_flags = quirk->data.write_flags = 1;
|
||||
quirk->data.address_match = 0x88000;
|
||||
quirk->data.address_mask = PCIE_CONFIG_SPACE_SIZE - 1;
|
||||
quirk->data.bar = nr;
|
||||
|
||||
memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_nvidia_bar0_88000_quirk, quirk,
|
||||
"vfio-nvidia-bar0-88000-quirk",
|
||||
TARGET_PAGE_ALIGN(PCIE_CONFIG_SPACE_SIZE));
|
||||
memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_generic_quirk,
|
||||
quirk, "vfio-nvidia-bar0-88000-quirk",
|
||||
TARGET_PAGE_ALIGN(quirk->data.address_mask + 1));
|
||||
memory_region_add_subregion_overlap(&vdev->bars[nr].mem,
|
||||
0x88000 & TARGET_PAGE_MASK,
|
||||
&quirk->mem, 1);
|
||||
quirk->data.address_match & TARGET_PAGE_MASK,
|
||||
&quirk->mem, 1);
|
||||
|
||||
QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);
|
||||
|
||||
@ -1661,51 +1684,6 @@ static void vfio_probe_nvidia_bar0_88000_quirk(VFIODevice *vdev, int nr)
|
||||
/*
|
||||
* And here's the same for BAR0 offset 0x1800...
|
||||
*/
|
||||
static uint64_t vfio_nvidia_bar0_1800_quirk_read(void *opaque,
|
||||
hwaddr addr, unsigned size)
|
||||
{
|
||||
VFIOQuirk *quirk = opaque;
|
||||
VFIODevice *vdev = quirk->vdev;
|
||||
hwaddr base = 0x1800 & TARGET_PAGE_MASK;
|
||||
hwaddr offset = 0x1800 & ~TARGET_PAGE_MASK;
|
||||
uint64_t data = vfio_bar_read(&vdev->bars[0], addr + base, size);
|
||||
|
||||
if (ranges_overlap(addr, size, offset, PCI_CONFIG_SPACE_SIZE)) {
|
||||
data = vfio_pci_read_config(&vdev->pdev, addr - offset, size);
|
||||
|
||||
DPRINTF("%s(%04x:%02x:%02x.%x:BAR0+0x%"HWADDR_PRIx", %d) = 0x%"
|
||||
PRIx64"\n", __func__, vdev->host.domain, vdev->host.bus,
|
||||
vdev->host.slot, vdev->host.function, addr + base, size, data);
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
static void vfio_nvidia_bar0_1800_quirk_write(void *opaque, hwaddr addr,
|
||||
uint64_t data, unsigned size)
|
||||
{
|
||||
VFIOQuirk *quirk = opaque;
|
||||
VFIODevice *vdev = quirk->vdev;
|
||||
hwaddr base = 0x1800 & TARGET_PAGE_MASK;
|
||||
hwaddr offset = 0x1800 & ~TARGET_PAGE_MASK;
|
||||
|
||||
if (ranges_overlap(addr, size, offset, PCI_CONFIG_SPACE_SIZE)) {
|
||||
vfio_pci_write_config(&vdev->pdev, addr - offset, data, size);
|
||||
|
||||
DPRINTF("%s(%04x:%02x:%02x.%x:BAR0+0x%"HWADDR_PRIx", 0x%"
|
||||
PRIx64", %d)\n", __func__, vdev->host.domain, vdev->host.bus,
|
||||
vdev->host.slot, vdev->host.function, addr + base, data, size);
|
||||
} else {
|
||||
vfio_bar_write(&vdev->bars[0], addr + base, data, size);
|
||||
}
|
||||
}
|
||||
|
||||
static const MemoryRegionOps vfio_nvidia_bar0_1800_quirk = {
|
||||
.read = vfio_nvidia_bar0_1800_quirk_read,
|
||||
.write = vfio_nvidia_bar0_1800_quirk_write,
|
||||
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||
};
|
||||
|
||||
static void vfio_probe_nvidia_bar0_1800_quirk(VFIODevice *vdev, int nr)
|
||||
{
|
||||
PCIDevice *pdev = &vdev->pdev;
|
||||
@ -1722,13 +1700,17 @@ static void vfio_probe_nvidia_bar0_1800_quirk(VFIODevice *vdev, int nr)
|
||||
|
||||
quirk = g_malloc0(sizeof(*quirk));
|
||||
quirk->vdev = vdev;
|
||||
quirk->data.flags = quirk->data.read_flags = quirk->data.write_flags = 1;
|
||||
quirk->data.address_match = 0x1800;
|
||||
quirk->data.address_mask = PCI_CONFIG_SPACE_SIZE - 1;
|
||||
quirk->data.bar = nr;
|
||||
|
||||
memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_nvidia_bar0_1800_quirk, quirk,
|
||||
memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_generic_quirk, quirk,
|
||||
"vfio-nvidia-bar0-1800-quirk",
|
||||
TARGET_PAGE_ALIGN(PCI_CONFIG_SPACE_SIZE));
|
||||
TARGET_PAGE_ALIGN(quirk->data.address_mask + 1));
|
||||
memory_region_add_subregion_overlap(&vdev->bars[nr].mem,
|
||||
0x1800 & TARGET_PAGE_MASK,
|
||||
&quirk->mem, 1);
|
||||
quirk->data.address_match & TARGET_PAGE_MASK,
|
||||
&quirk->mem, 1);
|
||||
|
||||
QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);
|
||||
|
||||
@ -1768,8 +1750,8 @@ static void vfio_vga_quirk_teardown(VFIODevice *vdev)
|
||||
|
||||
static void vfio_bar_quirk_setup(VFIODevice *vdev, int nr)
|
||||
{
|
||||
vfio_probe_ati_4010_quirk(vdev, nr);
|
||||
vfio_probe_ati_f10_quirk(vdev, nr);
|
||||
vfio_probe_ati_bar4_window_quirk(vdev, nr);
|
||||
vfio_probe_ati_bar2_4000_quirk(vdev, nr);
|
||||
vfio_probe_nvidia_bar5_window_quirk(vdev, nr);
|
||||
vfio_probe_nvidia_bar0_88000_quirk(vdev, nr);
|
||||
vfio_probe_nvidia_bar0_1800_quirk(vdev, nr);
|
||||
@ -2270,11 +2252,14 @@ static void vfio_map_bar(VFIODevice *vdev, int nr)
|
||||
}
|
||||
|
||||
pci_bar = le32_to_cpu(pci_bar);
|
||||
type = pci_bar & (pci_bar & PCI_BASE_ADDRESS_SPACE_IO ?
|
||||
~PCI_BASE_ADDRESS_IO_MASK : ~PCI_BASE_ADDRESS_MEM_MASK);
|
||||
bar->ioport = (pci_bar & PCI_BASE_ADDRESS_SPACE_IO);
|
||||
bar->mem64 = bar->ioport ? 0 : (pci_bar & PCI_BASE_ADDRESS_MEM_TYPE_64);
|
||||
type = pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK :
|
||||
~PCI_BASE_ADDRESS_MEM_MASK);
|
||||
|
||||
/* A "slow" read/write mapping underlies all BARs */
|
||||
memory_region_init_io(&bar->mem, OBJECT(vdev), &vfio_bar_ops, bar, name, size);
|
||||
memory_region_init_io(&bar->mem, OBJECT(vdev), &vfio_bar_ops,
|
||||
bar, name, size);
|
||||
pci_register_bar(&vdev->pdev, nr, type, &bar->mem);
|
||||
|
||||
/*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user