target/loongarch: Add CSRs definition
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-20-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Xiaojuan Yang
Richard Henderson
parent
d88b51dc26
commit
398cecb9c3
208
target/loongarch/cpu-csr.h
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208
target/loongarch/cpu-csr.h
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@ -0,0 +1,208 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* QEMU LoongArch CSRs
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#ifndef LOONGARCH_CPU_CSR_H
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#define LOONGARCH_CPU_CSR_H
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#include "hw/registerfields.h"
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/* Base on kernal definitions: arch/loongarch/include/asm/loongarch.h */
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/* Basic CSRs */
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#define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
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#define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */
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FIELD(CSR_PRMD, PPLV, 0, 2)
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FIELD(CSR_PRMD, PIE, 2, 1)
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FIELD(CSR_PRMD, PWE, 3, 1)
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#define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */
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FIELD(CSR_EUEN, FPE, 0, 1)
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FIELD(CSR_EUEN, SXE, 1, 1)
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FIELD(CSR_EUEN, ASXE, 2, 1)
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FIELD(CSR_EUEN, BTE, 3, 1)
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#define LOONGARCH_CSR_MISC 0x3 /* Misc config */
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FIELD(CSR_MISC, VA32, 0, 4)
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FIELD(CSR_MISC, DRDTL, 4, 4)
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FIELD(CSR_MISC, RPCNTL, 8, 4)
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FIELD(CSR_MISC, ALCL, 12, 4)
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FIELD(CSR_MISC, DWPL, 16, 3)
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#define LOONGARCH_CSR_ECFG 0x4 /* Exception config */
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FIELD(CSR_ECFG, LIE, 0, 13)
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FIELD(CSR_ECFG, VS, 16, 3)
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#define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
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FIELD(CSR_ESTAT, IS, 0, 13)
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FIELD(CSR_ESTAT, ECODE, 16, 6)
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FIELD(CSR_ESTAT, ESUBCODE, 22, 9)
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#define LOONGARCH_CSR_ERA 0x6 /* Exception return address */
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#define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */
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#define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */
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#define LOONGARCH_CSR_EENTRY 0xc /* Exception entry address */
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/* TLB related CSRs */
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#define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */
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FIELD(CSR_TLBIDX, INDEX, 0, 12)
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FIELD(CSR_TLBIDX, PS, 24, 6)
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FIELD(CSR_TLBIDX, NE, 31, 1)
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#define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */
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FIELD(CSR_TLBEHI, VPPN, 13, 35)
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#define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
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#define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */
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FIELD(TLBENTRY, V, 0, 1)
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FIELD(TLBENTRY, D, 1, 1)
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FIELD(TLBENTRY, PLV, 2, 2)
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FIELD(TLBENTRY, MAT, 4, 2)
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FIELD(TLBENTRY, G, 6, 1)
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FIELD(TLBENTRY, PPN, 12, 36)
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FIELD(TLBENTRY, NR, 61, 1)
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FIELD(TLBENTRY, NX, 62, 1)
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FIELD(TLBENTRY, RPLV, 63, 1)
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#define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */
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FIELD(CSR_ASID, ASID, 0, 10)
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FIELD(CSR_ASID, ASIDBITS, 16, 8)
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/* Page table base address when badv[47] = 0 */
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#define LOONGARCH_CSR_PGDL 0x19
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/* Page table base address when badv[47] = 1 */
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#define LOONGARCH_CSR_PGDH 0x1a
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#define LOONGARCH_CSR_PGD 0x1b /* Page table base address */
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/* Page walk controller's low addr */
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#define LOONGARCH_CSR_PWCL 0x1c
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FIELD(CSR_PWCL, PTBASE, 0, 5)
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FIELD(CSR_PWCL, PTWIDTH, 5, 5)
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FIELD(CSR_PWCL, DIR1_BASE, 10, 5)
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FIELD(CSR_PWCL, DIR1_WIDTH, 15, 5)
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FIELD(CSR_PWCL, DIR2_BASE, 20, 5)
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FIELD(CSR_PWCL, DIR2_WIDTH, 25, 5)
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FIELD(CSR_PWCL, PTEWIDTH, 30, 2)
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/* Page walk controller's high addr */
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#define LOONGARCH_CSR_PWCH 0x1d
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FIELD(CSR_PWCH, DIR3_BASE, 0, 6)
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FIELD(CSR_PWCH, DIR3_WIDTH, 6, 6)
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FIELD(CSR_PWCH, DIR4_BASE, 12, 6)
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FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6)
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#define LOONGARCH_CSR_STLBPS 0x1e /* Stlb page size */
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FIELD(CSR_STLBPS, PS, 0, 5)
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#define LOONGARCH_CSR_RVACFG 0x1f /* Reduced virtual address config */
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FIELD(CSR_RVACFG, RBITS, 0, 4)
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/* Config CSRs */
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#define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */
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#define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */
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FIELD(CSR_PRCFG1, SAVE_NUM, 0, 4)
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FIELD(CSR_PRCFG1, TIMER_BITS, 4, 8)
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FIELD(CSR_PRCFG1, VSMAX, 12, 3)
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#define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */
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#define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */
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FIELD(CSR_PRCFG3, TLB_TYPE, 0, 4)
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FIELD(CSR_PRCFG3, MTLB_ENTRY, 4, 8)
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FIELD(CSR_PRCFG3, STLB_WAYS, 12, 8)
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FIELD(CSR_PRCFG3, STLB_SETS, 20, 8)
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/*
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* Save registers count can read from PRCFG1.SAVE_NUM
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* The Min count is 1. Max count is 15.
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*/
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#define LOONGARCH_CSR_SAVE(N) (0x30 + N)
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/* Timer CSRs */
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#define LOONGARCH_CSR_TID 0x40 /* Timer ID */
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#define LOONGARCH_CSR_TCFG 0x41 /* Timer config */
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FIELD(CSR_TCFG, EN, 0, 1)
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FIELD(CSR_TCFG, PERIODIC, 1, 1)
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FIELD(CSR_TCFG, INIT_VAL, 2, 46)
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#define LOONGARCH_CSR_TVAL 0x42 /* Timer ticks remain */
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#define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */
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#define LOONGARCH_CSR_TICLR 0x44 /* Timer interrupt clear */
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/* LLBCTL CSRs */
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#define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */
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FIELD(CSR_LLBCTL, ROLLB, 0, 1)
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FIELD(CSR_LLBCTL, WCLLB, 1, 1)
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FIELD(CSR_LLBCTL, KLO, 2, 1)
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/* Implement dependent */
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#define LOONGARCH_CSR_IMPCTL1 0x80 /* LoongArch config1 */
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#define LOONGARCH_CSR_IMPCTL2 0x81 /* LoongArch config2*/
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/* TLB Refill CSRs */
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#define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception address */
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#define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */
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#define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */
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#define LOONGARCH_CSR_TLBRSAVE 0x8b /* KScratch for TLB refill */
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FIELD(CSR_TLBRERA, ISTLBR, 0, 1)
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FIELD(CSR_TLBRERA, PC, 2, 62)
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#define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */
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#define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */
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#define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */
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FIELD(CSR_TLBREHI, PS, 0, 6)
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FIELD(CSR_TLBREHI, VPPN, 13, 35)
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#define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */
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FIELD(CSR_TLBRPRMD, PPLV, 0, 2)
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FIELD(CSR_TLBRPRMD, PIE, 2, 1)
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FIELD(CSR_TLBRPRMD, PWE, 4, 1)
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/* Machine Error CSRs */
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#define LOONGARCH_CSR_MERRCTL 0x90 /* ERRCTL */
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FIELD(CSR_MERRCTL, ISMERR, 0, 1)
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#define LOONGARCH_CSR_MERRINFO1 0x91
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#define LOONGARCH_CSR_MERRINFO2 0x92
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#define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception base */
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#define LOONGARCH_CSR_MERRERA 0x94 /* MError exception PC */
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#define LOONGARCH_CSR_MERRSAVE 0x95 /* KScratch for error exception */
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#define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */
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/* Direct map windows CSRs*/
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#define LOONGARCH_CSR_DMW(N) (0x180 + N)
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FIELD(CSR_DMW, PLV0, 0, 1)
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FIELD(CSR_DMW, PLV1, 1, 1)
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FIELD(CSR_DMW, PLV2, 2, 1)
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FIELD(CSR_DMW, PLV3, 3, 1)
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FIELD(CSR_DMW, MAT, 4, 2)
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FIELD(CSR_DMW, VSEG, 60, 4)
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#define dmw_va2pa(va) \
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(va & MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS))
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/* Debug CSRs */
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#define LOONGARCH_CSR_DBG 0x500 /* debug config */
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FIELD(CSR_DBG, DST, 0, 1)
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FIELD(CSR_DBG, DREV, 1, 7)
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FIELD(CSR_DBG, DEI, 8, 1)
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FIELD(CSR_DBG, DCL, 9, 1)
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FIELD(CSR_DBG, DFW, 10, 1)
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FIELD(CSR_DBG, DMW, 11, 1)
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FIELD(CSR_DBG, ECODE, 16, 6)
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#define LOONGARCH_CSR_DERA 0x501 /* Debug era */
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#define LOONGARCH_CSR_DSAVE 0x502 /* Debug save */
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#endif /* LOONGARCH_CPU_CSR_H */
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@ -16,6 +16,7 @@
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#include "cpu.h"
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#include "internals.h"
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#include "fpu/softfloat-helpers.h"
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#include "cpu-csr.h"
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const char * const regnames[32] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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@ -167,6 +168,8 @@ static void loongarch_la464_initfn(Object *obj)
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data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14);
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data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 6);
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env->cpucfg[20] = data;
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env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
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}
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static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
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@ -196,6 +199,44 @@ static void loongarch_cpu_reset(DeviceState *dev)
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env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
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env->fcsr0 = 0x0;
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int n;
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/* Set csr registers value after reset */
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1);
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1);
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env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0);
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env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0);
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env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0);
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env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0);
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env->CSR_MISC = 0;
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env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0);
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env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0);
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env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2));
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env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0);
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env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
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env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0);
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env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
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env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);
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env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2);
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env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63);
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env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
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env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
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for (n = 0; n < 4; n++) {
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env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0);
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env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0);
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env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0);
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env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0);
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}
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restore_fp_status(env);
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cs->exception_index = -1;
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}
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@ -172,6 +172,15 @@ FIELD(CPUCFG20, L3IU_WAYS, 0, 16)
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FIELD(CPUCFG20, L3IU_SETS, 16, 8)
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FIELD(CPUCFG20, L3IU_SIZE, 24, 7)
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/*CSR_CRMD */
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FIELD(CSR_CRMD, PLV, 0, 2)
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FIELD(CSR_CRMD, IE, 2, 1)
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FIELD(CSR_CRMD, DA, 3, 1)
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FIELD(CSR_CRMD, PG, 4, 1)
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FIELD(CSR_CRMD, DATF, 5, 2)
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FIELD(CSR_CRMD, DATM, 7, 2)
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FIELD(CSR_CRMD, WE, 9, 1)
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extern const char * const regnames[32];
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extern const char * const fregnames[32];
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@ -192,6 +201,61 @@ typedef struct CPUArchState {
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uint64_t llval;
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uint64_t badaddr;
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/* LoongArch CSRs */
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uint64_t CSR_CRMD;
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uint64_t CSR_PRMD;
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uint64_t CSR_EUEN;
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uint64_t CSR_MISC;
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uint64_t CSR_ECFG;
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uint64_t CSR_ESTAT;
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uint64_t CSR_ERA;
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uint64_t CSR_BADV;
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uint64_t CSR_BADI;
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uint64_t CSR_EENTRY;
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uint64_t CSR_TLBIDX;
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uint64_t CSR_TLBEHI;
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uint64_t CSR_TLBELO0;
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uint64_t CSR_TLBELO1;
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uint64_t CSR_ASID;
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uint64_t CSR_PGDL;
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uint64_t CSR_PGDH;
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uint64_t CSR_PGD;
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uint64_t CSR_PWCL;
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uint64_t CSR_PWCH;
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uint64_t CSR_STLBPS;
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uint64_t CSR_RVACFG;
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uint64_t CSR_PRCFG1;
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uint64_t CSR_PRCFG2;
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uint64_t CSR_PRCFG3;
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uint64_t CSR_SAVE[16];
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uint64_t CSR_TID;
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uint64_t CSR_TCFG;
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uint64_t CSR_TVAL;
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uint64_t CSR_CNTC;
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uint64_t CSR_TICLR;
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uint64_t CSR_LLBCTL;
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uint64_t CSR_IMPCTL1;
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uint64_t CSR_IMPCTL2;
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uint64_t CSR_TLBRENTRY;
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uint64_t CSR_TLBRBADV;
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uint64_t CSR_TLBRERA;
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uint64_t CSR_TLBRSAVE;
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uint64_t CSR_TLBRELO0;
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uint64_t CSR_TLBRELO1;
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uint64_t CSR_TLBREHI;
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uint64_t CSR_TLBRPRMD;
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uint64_t CSR_MERRCTL;
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uint64_t CSR_MERRINFO1;
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uint64_t CSR_MERRINFO2;
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uint64_t CSR_MERRENTRY;
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uint64_t CSR_MERRERA;
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uint64_t CSR_MERRSAVE;
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uint64_t CSR_CTAG;
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uint64_t CSR_DMW[4];
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uint64_t CSR_DBG;
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uint64_t CSR_DERA;
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uint64_t CSR_DSAVE;
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} CPULoongArchState;
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/**
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