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target/sparc: Move BMASK to decodetree

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Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-05 09:01:34 -07:00
parent 9e20ca9409
commit 39ca3490f8
2 changed files with 15 additions and 9 deletions
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2
target/sparc/insns.decode
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@ -255,6 +255,8 @@ RETRY 10 00001 111110 00000 0 0000000000000
ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r
ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r
BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r
]
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
}

22
target/sparc/translate.c
View File

@ -4264,6 +4264,18 @@ static void gen_op_alignaddrl(TCGv dst, TCGv s1, TCGv s2)
TRANS(ALIGNADDR, VIS1, do_rrr, a, gen_op_alignaddr)
TRANS(ALIGNADDRL, VIS1, do_rrr, a, gen_op_alignaddrl)
static void gen_op_bmask(TCGv dst, TCGv s1, TCGv s2)
{
#ifdef TARGET_SPARC64
tcg_gen_add_tl(dst, s1, s2);
tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, dst, 32, 32);
#else
g_assert_not_reached();
#endif
}
TRANS(BMASK, VIS2, do_rrr, a, gen_op_bmask)
static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u)
{
TCGv dst, src1, src2;
@ -4803,7 +4815,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
{
unsigned int opc, rs1, rs2, rd;
TCGv cpu_src1 __attribute__((unused));
TCGv cpu_src2 __attribute__((unused));
TCGv_i32 cpu_src1_32, cpu_src2_32;
TCGv_i64 cpu_src1_64, cpu_src2_64;
TCGv_i32 cpu_dst_32 __attribute__((unused));
@ -5168,15 +5179,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x014: /* VIS I array32 */
case 0x018: /* VIS I alignaddr */
case 0x01a: /* VIS I alignaddrl */
g_assert_not_reached(); /* in decodetree */
case 0x019: /* VIS II bmask */
CHECK_FPU_FEATURE(dc, VIS2);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
gen_store_gpr(dc, rd, cpu_dst);
break;
g_assert_not_reached(); /* in decodetree */
case 0x020: /* VIS I fcmple16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);