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tcg/loongarch64: Implement add/sub ops

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The neg_i{32,64} ops is fully expressible with sub, so omitted for
simplicity.

Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-18-git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
WANG Xuerui 2021-12-21 13:40:51 +08:00 committed by Richard Henderson
parent a164010b05
commit 39f54ce5c4
2 changed files with 40 additions and 0 deletions
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2
tcg/loongarch64/tcg-target-con-set.h
View File

@ -18,6 +18,8 @@ C_O0_I1(r)
C_O1_I1(r, r)
C_O1_I2(r, r, rC)
C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)
C_O1_I2(r, r, rU)
C_O1_I2(r, r, rW)
C_O1_I2(r, 0, rZ)
C_O1_I2(r, rZ, rN)

38
tcg/loongarch64/tcg-target.c.inc
View File

@ -687,6 +687,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
case INDEX_op_add_i32:
if (c2) {
tcg_out_opc_addi_w(s, a0, a1, a2);
} else {
tcg_out_opc_add_w(s, a0, a1, a2);
}
break;
case INDEX_op_add_i64:
if (c2) {
tcg_out_opc_addi_d(s, a0, a1, a2);
} else {
tcg_out_opc_add_d(s, a0, a1, a2);
}
break;
case INDEX_op_sub_i32:
if (c2) {
tcg_out_opc_addi_w(s, a0, a1, -a2);
} else {
tcg_out_opc_sub_w(s, a0, a1, a2);
}
break;
case INDEX_op_sub_i64:
if (c2) {
tcg_out_opc_addi_d(s, a0, a1, -a2);
} else {
tcg_out_opc_sub_d(s, a0, a1, a2);
}
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@ -748,6 +778,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_rotr_i64:
return C_O1_I2(r, r, ri);
case INDEX_op_add_i32:
case INDEX_op_add_i64:
return C_O1_I2(r, r, rI);
case INDEX_op_and_i32:
case INDEX_op_and_i64:
case INDEX_op_nor_i32:
@ -770,6 +804,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
/* Must deposit into the same register as input */
return C_O1_I2(r, 0, rZ);
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
return C_O1_I2(r, rZ, rN);
default:
g_assert_not_reached();
}