hw/block/pflash_cfi01: Add missing DeviceReset() handler
To avoid incoherent states when the machine resets (see bug report below), add the device reset callback. A "system reset" sets the device state machine in READ_ARRAY mode and, after some delay, set the SR.7 READY bit. Since we do not model timings, we set the SR.7 bit directly. Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1678713 Reported-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> [Laszlo Ersek: Regression tested EDK2 OVMF IA32X64, ArmVirtQemu Aarch64 https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg04373.html] Message-Id: <20190718104837.13905-2-philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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@ -865,6 +865,24 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
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pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */
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}
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static void pflash_cfi01_system_reset(DeviceState *dev)
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{
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PFlashCFI01 *pfl = PFLASH_CFI01(dev);
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/*
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* The command 0x00 is not assigned by the CFI open standard,
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* but QEMU historically uses it for the READ_ARRAY command (0xff).
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*/
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pfl->cmd = 0x00;
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pfl->wcycle = 0;
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memory_region_rom_device_set_romd(&pfl->mem, true);
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/*
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* The WSM ready timer occurs at most 150ns after system reset.
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* This model deliberately ignores this delay.
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*/
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pfl->status = 0x80;
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}
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static Property pflash_cfi01_properties[] = {
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DEFINE_PROP_DRIVE("drive", PFlashCFI01, blk),
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/* num-blocks is the number of blocks actually visible to the guest,
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@ -909,6 +927,7 @@ static void pflash_cfi01_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = pflash_cfi01_system_reset;
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dc->realize = pflash_cfi01_realize;
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dc->props = pflash_cfi01_properties;
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dc->vmsd = &vmstate_pflash;
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