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target-arm: Add support for 'Standard FPSCR Value' as used by Neon

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Add support to the ARM helper routines for a second fp_status value
which should be used for operations which the ARM ARM indicates use
"ARM standard floating-point arithmetic" rather than being controlled
by the rounding/flush/NaN settings in the FPSCR.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Peter Maydell 2011-01-14 20:39:18 +01:00 committed by Aurelien Jarno
parent 9ea62f571c
commit 3a492f3a60
2 changed files with 18 additions and 0 deletions
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13
target-arm/cpu.h
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@ -173,7 +173,20 @@ typedef struct CPUARMState {
/* scratch space when Tn are not sufficient. */ /* scratch space when Tn are not sufficient. */
uint32_t scratch[8]; uint32_t scratch[8];
/* fp_status is the "normal" fp status. standard_fp_status retains
* values corresponding to the ARM "Standard FPSCR Value", ie
* default-NaN, flush-to-zero, round-to-nearest and is used by
* any operations (generally Neon) which the architecture defines
* as controlled by the standard FPSCR value rather than the FPSCR.
*
* To avoid having to transfer exception bits around, we simply
* say that the FPSCR cumulative exception flags are the logical
* OR of the flags in the two fp statuses. This relies on the
* only thing which needs to read the exception flags being
* an explicit FPSCR read.
*/
float_status fp_status; float_status fp_status;
float_status standard_fp_status;
} vfp; } vfp;
uint32_t exclusive_addr; uint32_t exclusive_addr;
uint32_t exclusive_val; uint32_t exclusive_val;

5
target-arm/helper.c
View File

@ -237,6 +237,9 @@ void cpu_reset(CPUARMState *env)
env->vfp.xregs[ARM_VFP_FPEXC] = 0; env->vfp.xregs[ARM_VFP_FPEXC] = 0;
env->cp15.c2_base_mask = 0xffffc000u; env->cp15.c2_base_mask = 0xffffc000u;
#endif #endif
set_flush_to_zero(1, &env->vfp.standard_fp_status);
set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
set_default_nan_mode(1, &env->vfp.standard_fp_status);
tlb_flush(env, 1); tlb_flush(env, 1);
} }
@ -2256,6 +2259,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
| (env->vfp.vec_len << 16) | (env->vfp.vec_len << 16)
| (env->vfp.vec_stride << 20); | (env->vfp.vec_stride << 20);
i = get_float_exception_flags(&env->vfp.fp_status); i = get_float_exception_flags(&env->vfp.fp_status);
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
fpscr |= vfp_exceptbits_from_host(i); fpscr |= vfp_exceptbits_from_host(i);
return fpscr; return fpscr;
} }
@ -2323,6 +2327,7 @@ void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
i = vfp_exceptbits_to_host(val); i = vfp_exceptbits_to_host(val);
set_float_exception_flags(i, &env->vfp.fp_status); set_float_exception_flags(i, &env->vfp.fp_status);
set_float_exception_flags(0, &env->vfp.standard_fp_status);
} }
void vfp_set_fpscr(CPUState *env, uint32_t val) void vfp_set_fpscr(CPUState *env, uint32_t val)