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microblaze: Compute masks for alignment checks at translation time.

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Thanks to Blue Swirl for reporting.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Edgar E. Iglesias 2009-09-03 22:28:21 +02:00
parent faed1c2a23
commit 3aa8098843
2 changed files with 6 additions and 15 deletions
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17
target-microblaze/op_helper.c
View File

@ -206,27 +206,18 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
return 0; return 0;
} }
void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t size) void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
{ {
uint32_t mask;
switch (size) {
case 4: mask = 3; break;
case 2: mask = 1; break;
default:
case 1: mask = 0; break;
}
if (addr & mask) { if (addr & mask) {
qemu_log("unaligned access addr=%x size=%d, wr=%d\n", qemu_log("unaligned access addr=%x mask=%x, wr=%d\n",
addr, size, wr); addr, mask, wr);
if (!(env->sregs[SR_MSR] & MSR_EE)) { if (!(env->sregs[SR_MSR] & MSR_EE)) {
return; return;
} }
env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \ env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
| (dr & 31) << 5; | (dr & 31) << 5;
if (size == 4) { if (mask == 3) {
env->sregs[SR_ESR] |= 1 << 11; env->sregs[SR_ESR] |= 1 << 11;
} }
helper_raise_exception(EXCP_HW_EXCP); helper_raise_exception(EXCP_HW_EXCP);

4
target-microblaze/translate.c
View File

@ -814,7 +814,7 @@ static void dec_load(DisasContext *dc)
/* Verify alignment if needed. */ /* Verify alignment if needed. */
if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
gen_helper_memalign(*addr, tcg_const_tl(dc->rd), gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
tcg_const_tl(0), tcg_const_tl(size)); tcg_const_tl(0), tcg_const_tl(size - 1));
} }
if (dc->rd) { if (dc->rd) {
@ -858,7 +858,7 @@ static void dec_store(DisasContext *dc)
/* Verify alignment if needed. */ /* Verify alignment if needed. */
if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
gen_helper_memalign(*addr, tcg_const_tl(dc->rd), gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
tcg_const_tl(1), tcg_const_tl(size)); tcg_const_tl(1), tcg_const_tl(size - 1));
} }
gen_store(dc, *addr, cpu_R[dc->rd], size); gen_store(dc, *addr, cpu_R[dc->rd], size);