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cpu defs: use Intel flag names for Intel models (v2)

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Use 'i64' instead of 'lm' and 'xd' instead of 'nx' on Intel models.

The flags have different names on Intel docs, so use those names for clarity.

This is based on a previous patch from John Cooper where this was introduced
with many other changes at the same time. Original John's patch submission is
at Message-ID: <4DDAD5E7.2020002@redhat.com>, <http://marc.info/?l=qemu-devel&m=130618871926030>.

Changes v1 -> v2:
 - Rebase patch against latest Qemu git tree

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Eduardo Habkost 2012-02-17 14:41:21 -02:00 committed by Anthony Liguori
parent f370be3c50
commit 3ac8ebfe1c
2 changed files with 5 additions and 5 deletions
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6
sysconfigs/target/target-x86_64.conf
View File

@ -9,7 +9,7 @@
stepping = "3"
feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
feature_ecx = "ssse3 sse3"
extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
extfeature_ecx = "lahf_lm"
xlevel = "0x8000000A"
model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)"
@ -23,7 +23,7 @@
stepping = "3"
feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
feature_ecx = "sse4.1 cx16 ssse3 sse3"
extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
extfeature_ecx = "lahf_lm"
xlevel = "0x8000000A"
model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)"
@ -37,7 +37,7 @@
stepping = "3"
feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
extfeature_ecx = "lahf_lm"
xlevel = "0x8000000A"
model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"

4
target-i386/cpuid.c
View File

@ -59,9 +59,9 @@ static const char *ext2_feature_name[] = {
"cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
"mtrr", "pge", "mca", "cmov",
"pat", "pse36", NULL, NULL /* Linux mp */,
"nx" /* Intel xd */, NULL, "mmxext", "mmx",
"nx|xd", NULL, "mmxext", "mmx",
"fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
NULL, "lm" /* Intel 64 */, "3dnowext", "3dnow",
NULL, "lm|i64", "3dnowext", "3dnow",
};
static const char *ext3_feature_name[] = {
"lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,