ppc4xx_i2c: QOMify
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
parent
65ca801bf4
commit
3b09bb0fb9
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@ -59,8 +59,6 @@ struct ppc4xx_bd_info_t {
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ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
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ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
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uint32_t flags);
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uint32_t flags);
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void ppc405_i2c_init(hwaddr base, qemu_irq irq);
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CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
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CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
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MemoryRegion ram_memories[4],
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MemoryRegion ram_memories[4],
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hwaddr ram_bases[4],
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hwaddr ram_bases[4],
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@ -28,6 +28,7 @@
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#include "hw/hw.h"
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#include "hw/hw.h"
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#include "hw/ppc/ppc.h"
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#include "hw/ppc/ppc.h"
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#include "hw/boards.h"
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#include "hw/boards.h"
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#include "hw/i2c/ppc4xx_i2c.h"
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#include "ppc405.h"
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#include "ppc405.h"
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#include "hw/char/serial.h"
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#include "hw/char/serial.h"
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#include "qemu/timer.h"
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#include "qemu/timer.h"
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@ -1663,7 +1664,7 @@ CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
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DEVICE_BIG_ENDIAN);
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DEVICE_BIG_ENDIAN);
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}
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}
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/* IIC controller */
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/* IIC controller */
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ppc405_i2c_init(0xef600500, pic[2]);
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sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);
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/* GPIO */
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/* GPIO */
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ppc405_gpio_init(0xef600700);
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ppc405_gpio_init(0xef600700);
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/* CPU control */
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/* CPU control */
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@ -2010,7 +2011,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
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dma_irqs[3] = pic[8];
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dma_irqs[3] = pic[8];
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ppc405_dma_init(env, dma_irqs);
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ppc405_dma_init(env, dma_irqs);
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/* IIC controller */
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/* IIC controller */
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ppc405_i2c_init(0xef600500, pic[2]);
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sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);
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/* GPIO */
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/* GPIO */
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ppc405_gpio_init(0xef600700);
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ppc405_gpio_init(0xef600700);
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/* Serial ports */
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/* Serial ports */
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@ -27,42 +27,20 @@
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#include "qemu-common.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "hw/hw.h"
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#include "exec/address-spaces.h"
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#include "hw/i2c/ppc4xx_i2c.h"
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#include "hw/ppc/ppc.h"
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#include "ppc405.h"
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/*#define DEBUG_I2C*/
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/*#define DEBUG_I2C*/
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typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
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#define PPC4xx_I2C_MEM_SIZE 0x11
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struct ppc4xx_i2c_t {
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qemu_irq irq;
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MemoryRegion iomem;
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uint8_t mdata;
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uint8_t lmadr;
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uint8_t hmadr;
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uint8_t cntl;
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uint8_t mdcntl;
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uint8_t sts;
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uint8_t extsts;
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uint8_t sdata;
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uint8_t lsadr;
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uint8_t hsadr;
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uint8_t clkdiv;
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uint8_t intrmsk;
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uint8_t xfrcnt;
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uint8_t xtcntlss;
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uint8_t directcntl;
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};
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static uint32_t ppc4xx_i2c_readb(void *opaque, hwaddr addr)
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static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size)
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{
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{
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ppc4xx_i2c_t *i2c;
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PPC4xxI2CState *i2c = PPC4xx_I2C(opaque);
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uint32_t ret;
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uint64_t ret;
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#ifdef DEBUG_I2C
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#ifdef DEBUG_I2C
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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#endif
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i2c = opaque;
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switch (addr) {
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switch (addr) {
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case 0x00:
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case 0x00:
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/*i2c_readbyte(&i2c->mdata);*/
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/*i2c_readbyte(&i2c->mdata);*/
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@ -115,22 +93,20 @@ static uint32_t ppc4xx_i2c_readb(void *opaque, hwaddr addr)
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break;
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break;
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}
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}
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#ifdef DEBUG_I2C
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#ifdef DEBUG_I2C
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printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
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printf("%s: addr " TARGET_FMT_plx " %02" PRIx64 "\n", __func__, addr, ret);
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#endif
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#endif
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return ret;
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return ret;
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}
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}
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static void ppc4xx_i2c_writeb(void *opaque,
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static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value,
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hwaddr addr, uint32_t value)
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unsigned int size)
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{
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{
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ppc4xx_i2c_t *i2c;
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PPC4xxI2CState *i2c = opaque;
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#ifdef DEBUG_I2C
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#ifdef DEBUG_I2C
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx64 "\n",
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value);
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__func__, addr, value);
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#endif
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#endif
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i2c = opaque;
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switch (addr) {
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switch (addr) {
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case 0x00:
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case 0x00:
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i2c->mdata = value;
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i2c->mdata = value;
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@ -181,71 +157,20 @@ static void ppc4xx_i2c_writeb(void *opaque,
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}
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}
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}
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}
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static uint32_t ppc4xx_i2c_readw(void *opaque, hwaddr addr)
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static const MemoryRegionOps ppc4xx_i2c_ops = {
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{
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.read = ppc4xx_i2c_readb,
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uint32_t ret;
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.write = ppc4xx_i2c_writeb,
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.valid.min_access_size = 1,
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#ifdef DEBUG_I2C
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.valid.max_access_size = 4,
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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.impl.min_access_size = 1,
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#endif
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.impl.max_access_size = 1,
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ret = ppc4xx_i2c_readb(opaque, addr) << 8;
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ret |= ppc4xx_i2c_readb(opaque, addr + 1);
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return ret;
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}
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static void ppc4xx_i2c_writew(void *opaque,
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hwaddr addr, uint32_t value)
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{
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#ifdef DEBUG_I2C
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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ppc4xx_i2c_writeb(opaque, addr, value >> 8);
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ppc4xx_i2c_writeb(opaque, addr + 1, value);
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}
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static uint32_t ppc4xx_i2c_readl(void *opaque, hwaddr addr)
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{
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uint32_t ret;
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#ifdef DEBUG_I2C
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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ret = ppc4xx_i2c_readb(opaque, addr) << 24;
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ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
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ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
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ret |= ppc4xx_i2c_readb(opaque, addr + 3);
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return ret;
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}
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static void ppc4xx_i2c_writel(void *opaque,
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hwaddr addr, uint32_t value)
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{
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#ifdef DEBUG_I2C
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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ppc4xx_i2c_writeb(opaque, addr, value >> 24);
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ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
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ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
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ppc4xx_i2c_writeb(opaque, addr + 3, value);
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}
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static const MemoryRegionOps i2c_ops = {
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.old_mmio = {
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.read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
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.write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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};
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static void ppc4xx_i2c_reset(void *opaque)
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static void ppc4xx_i2c_reset(DeviceState *s)
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{
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{
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ppc4xx_i2c_t *i2c;
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PPC4xxI2CState *i2c = PPC4xx_I2C(s);
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i2c = opaque;
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i2c->mdata = 0x00;
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i2c->mdata = 0x00;
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i2c->sdata = 0x00;
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i2c->sdata = 0x00;
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i2c->cntl = 0x00;
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i2c->cntl = 0x00;
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@ -257,16 +182,35 @@ static void ppc4xx_i2c_reset(void *opaque)
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i2c->directcntl = 0x0F;
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i2c->directcntl = 0x0F;
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}
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}
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void ppc405_i2c_init(hwaddr base, qemu_irq irq)
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static void ppc4xx_i2c_init(Object *o)
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{
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{
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ppc4xx_i2c_t *i2c;
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PPC4xxI2CState *s = PPC4xx_I2C(o);
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i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
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memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s,
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i2c->irq = irq;
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TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE);
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#ifdef DEBUG_I2C
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
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printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
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sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
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#endif
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s->bus = i2c_init_bus(DEVICE(s), "i2c");
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memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, "i2c", 0x011);
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memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
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qemu_register_reset(ppc4xx_i2c_reset, i2c);
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}
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}
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static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = ppc4xx_i2c_reset;
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}
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static const TypeInfo ppc4xx_i2c_type_info = {
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.name = TYPE_PPC4xx_I2C,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PPC4xxI2CState),
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.instance_init = ppc4xx_i2c_init,
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.class_init = ppc4xx_i2c_class_init,
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};
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static void ppc4xx_i2c_register_types(void)
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{
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type_register_static(&ppc4xx_i2c_type_info);
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}
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type_init(ppc4xx_i2c_register_types)
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@ -0,0 +1,61 @@
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/*
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* PPC4xx I2C controller emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef PPC4XX_I2C_H
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#define PPC4XX_I2C_H
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "hw/sysbus.h"
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#include "hw/i2c/i2c.h"
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#define TYPE_PPC4xx_I2C "ppc4xx-i2c"
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#define PPC4xx_I2C(obj) OBJECT_CHECK(PPC4xxI2CState, (obj), TYPE_PPC4xx_I2C)
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typedef struct PPC4xxI2CState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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I2CBus *bus;
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qemu_irq irq;
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MemoryRegion iomem;
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uint8_t mdata;
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uint8_t lmadr;
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uint8_t hmadr;
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uint8_t cntl;
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uint8_t mdcntl;
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uint8_t sts;
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uint8_t extsts;
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uint8_t sdata;
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uint8_t lsadr;
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uint8_t hsadr;
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uint8_t clkdiv;
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uint8_t intrmsk;
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uint8_t xfrcnt;
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uint8_t xtcntlss;
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uint8_t directcntl;
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} PPC4xxI2CState;
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#endif /* PPC4XX_I2C_H */
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