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target/sparc: Convert to 3-phase reset 

Convert the sparc CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-id: 20221124115023.2437291-18-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-11-24 11:50:20 +00:00
parent 9049383002
commit 3b4fff1bd5
2 changed files with 10 additions and 6 deletions
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4
target/sparc/cpu-qom.h
View File

@ -35,7 +35,7 @@ typedef struct sparc_def_t sparc_def_t;
/** /**
* SPARCCPUClass: * SPARCCPUClass:
* @parent_realize: The parent class' realize handler. * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler. * @parent_phases: The parent class' reset phase handlers.
* *
* A SPARC CPU model. * A SPARC CPU model.
*/ */
@ -45,7 +45,7 @@ struct SPARCCPUClass {
/*< public >*/ /*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
DeviceReset parent_reset; ResettablePhases parent_phases;
sparc_def_t *cpu_def; sparc_def_t *cpu_def;
}; };

12
target/sparc/cpu.c
View File

@ -28,14 +28,16 @@
//#define DEBUG_FEATURES //#define DEBUG_FEATURES
static void sparc_cpu_reset(DeviceState *dev) static void sparc_cpu_reset_hold(Object *obj)
{ {
CPUState *s = CPU(dev); CPUState *s = CPU(obj);
SPARCCPU *cpu = SPARC_CPU(s); SPARCCPU *cpu = SPARC_CPU(s);
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu); SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu);
CPUSPARCState *env = &cpu->env; CPUSPARCState *env = &cpu->env;
scc->parent_reset(dev); if (scc->parent_phases.hold) {
scc->parent_phases.hold(obj);
}
memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
env->cwp = 0; env->cwp = 0;
@ -889,12 +891,14 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, sparc_cpu_realizefn, device_class_set_parent_realize(dc, sparc_cpu_realizefn,
&scc->parent_realize); &scc->parent_realize);
device_class_set_props(dc, sparc_cpu_properties); device_class_set_props(dc, sparc_cpu_properties);
device_class_set_parent_reset(dc, sparc_cpu_reset, &scc->parent_reset); resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL,
&scc->parent_phases);
cc->class_by_name = sparc_cpu_class_by_name; cc->class_by_name = sparc_cpu_class_by_name;
cc->parse_features = sparc_cpu_parse_features; cc->parse_features = sparc_cpu_parse_features;