target-i386: kill cpu_T3
It is almost unused, and it is simpler to pass a TCG value directly to gen_shiftd_rm_T1_T3. This value is then written to t2 without going through a temporary register. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -64,7 +64,7 @@ static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst;
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static TCGv_i32 cpu_cc_op;
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static TCGv cpu_regs[CPU_NB_REGS];
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/* local temps */
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static TCGv cpu_T[2], cpu_T3;
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static TCGv cpu_T[2];
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/* local register indexes (only used inside old micro ops) */
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static TCGv cpu_tmp0, cpu_tmp4;
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static TCGv_ptr cpu_ptr0, cpu_ptr1;
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@ -1858,8 +1858,8 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
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}
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/* XXX: add faster immediate case */
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static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
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int is_right)
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static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
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int is_right, TCGv count)
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{
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int label1, label2, data_bits;
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target_ulong mask;
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@ -1883,10 +1883,8 @@ static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
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gen_op_mov_v_reg(ot, t0, op1);
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}
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tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
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tcg_gen_andi_tl(t2, count, mask);
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tcg_gen_mov_tl(t1, cpu_T[1]);
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tcg_gen_mov_tl(t2, cpu_T3);
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/* Must test zero case to avoid using undefined behaviour in TCG
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shifts. */
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@ -5583,12 +5581,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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gen_op_mov_TN_reg(ot, 1, reg);
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if (shift) {
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val = cpu_ldub_code(env, s->pc++);
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tcg_gen_movi_tl(cpu_T3, val);
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TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++));
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gen_shiftd_rm_T1(s, ot, opreg, op, imm);
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tcg_temp_free(imm);
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} else {
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tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]);
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gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]);
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}
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gen_shiftd_rm_T1_T3(s, ot, opreg, op);
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break;
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/************************/
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@ -7869,7 +7867,6 @@ static inline void gen_intermediate_code_internal(CPUX86State *env,
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cpu_T[0] = tcg_temp_new();
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cpu_T[1] = tcg_temp_new();
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cpu_A0 = tcg_temp_new();
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cpu_T3 = tcg_temp_new();
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cpu_tmp0 = tcg_temp_new();
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cpu_tmp1_i64 = tcg_temp_new_i64();
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