ppc440_uc: Basic emulation of PPC440 DMA controller
PPC440 SoCs such as the AMCC 460EX have a DMA controller which is used by AmigaOS on the sam460ex. Implement the parts used by AmigaOS so it can get further booting on the sam460ex machine. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
BALATON Zoltan
David Gibson
parent
d2179f70d3
commit
3c409c1927
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@ -21,6 +21,7 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
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hwaddr *ram_bases, hwaddr *ram_sizes,
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int do_init);
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void ppc4xx_ahb_init(CPUPPCState *env);
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void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
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void ppc460ex_pcie_init(CPUPPCState *env);
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#endif /* PPC440_H */
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@ -13,6 +13,7 @@
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#include "qemu/cutils.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "exec/address-spaces.h"
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@ -802,6 +803,227 @@ void ppc4xx_ahb_init(CPUPPCState *env)
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qemu_register_reset(ppc4xx_ahb_reset, ahb);
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}
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/*****************************************************************************/
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/* DMA controller */
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#define DMA0_CR_CE (1 << 31)
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#define DMA0_CR_PW (1 << 26 | 1 << 25)
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#define DMA0_CR_DAI (1 << 24)
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#define DMA0_CR_SAI (1 << 23)
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#define DMA0_CR_DEC (1 << 2)
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enum {
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DMA0_CR = 0x00,
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DMA0_CT,
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DMA0_SAH,
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DMA0_SAL,
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DMA0_DAH,
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DMA0_DAL,
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DMA0_SGH,
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DMA0_SGL,
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DMA0_SR = 0x20,
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DMA0_SGC = 0x23,
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DMA0_SLP = 0x25,
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DMA0_POL = 0x26,
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};
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typedef struct {
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uint32_t cr;
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uint32_t ct;
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uint64_t sa;
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uint64_t da;
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uint64_t sg;
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} PPC4xxDmaChnl;
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typedef struct {
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int base;
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PPC4xxDmaChnl ch[4];
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uint32_t sr;
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} PPC4xxDmaState;
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static uint32_t dcr_read_dma(void *opaque, int dcrn)
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{
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PPC4xxDmaState *dma = opaque;
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uint32_t val = 0;
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int addr = dcrn - dma->base;
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int chnl = addr / 8;
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switch (addr) {
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case 0x00 ... 0x1f:
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switch (addr % 8) {
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case DMA0_CR:
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val = dma->ch[chnl].cr;
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break;
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case DMA0_CT:
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val = dma->ch[chnl].ct;
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break;
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case DMA0_SAH:
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val = dma->ch[chnl].sa >> 32;
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break;
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case DMA0_SAL:
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val = dma->ch[chnl].sa;
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break;
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case DMA0_DAH:
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val = dma->ch[chnl].da >> 32;
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break;
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case DMA0_DAL:
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val = dma->ch[chnl].da;
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break;
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case DMA0_SGH:
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val = dma->ch[chnl].sg >> 32;
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break;
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case DMA0_SGL:
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val = dma->ch[chnl].sg;
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break;
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}
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break;
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case DMA0_SR:
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val = dma->sr;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
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__func__, dcrn, chnl, addr);
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}
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return val;
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}
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static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
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{
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PPC4xxDmaState *dma = opaque;
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int addr = dcrn - dma->base;
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int chnl = addr / 8;
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switch (addr) {
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case 0x00 ... 0x1f:
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switch (addr % 8) {
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case DMA0_CR:
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dma->ch[chnl].cr = val;
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if (val & DMA0_CR_CE) {
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int count = dma->ch[chnl].ct & 0xffff;
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if (count) {
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int width, i, sidx, didx;
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uint8_t *rptr, *wptr;
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hwaddr rlen, wlen;
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sidx = didx = 0;
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width = 1 << ((val & DMA0_CR_PW) >> 25);
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rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen, 0);
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wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, 1);
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if (rptr && wptr) {
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if (!(val & DMA0_CR_DEC) &&
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val & DMA0_CR_SAI && val & DMA0_CR_DAI) {
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/* optimise common case */
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memmove(wptr, rptr, count * width);
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sidx = didx = count * width;
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} else {
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/* do it the slow way */
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for (sidx = didx = i = 0; i < count; i++) {
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uint64_t v = ldn_le_p(rptr + sidx, width);
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stn_le_p(wptr + didx, width, v);
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if (val & DMA0_CR_SAI) {
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sidx += width;
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}
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if (val & DMA0_CR_DAI) {
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didx += width;
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}
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}
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}
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}
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if (wptr) {
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cpu_physical_memory_unmap(wptr, wlen, 1, didx);
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}
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if (wptr) {
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cpu_physical_memory_unmap(rptr, rlen, 0, sidx);
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}
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}
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}
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break;
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case DMA0_CT:
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dma->ch[chnl].ct = val;
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break;
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case DMA0_SAH:
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dma->ch[chnl].sa &= 0xffffffffULL;
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dma->ch[chnl].sa |= (uint64_t)val << 32;
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break;
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case DMA0_SAL:
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dma->ch[chnl].sa &= 0xffffffff00000000ULL;
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dma->ch[chnl].sa |= val;
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break;
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case DMA0_DAH:
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dma->ch[chnl].da &= 0xffffffffULL;
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dma->ch[chnl].da |= (uint64_t)val << 32;
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break;
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case DMA0_DAL:
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dma->ch[chnl].da &= 0xffffffff00000000ULL;
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dma->ch[chnl].da |= val;
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break;
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case DMA0_SGH:
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dma->ch[chnl].sg &= 0xffffffffULL;
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dma->ch[chnl].sg |= (uint64_t)val << 32;
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break;
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case DMA0_SGL:
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dma->ch[chnl].sg &= 0xffffffff00000000ULL;
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dma->ch[chnl].sg |= val;
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break;
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}
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break;
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case DMA0_SR:
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dma->sr &= ~val;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
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__func__, dcrn, chnl, addr);
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}
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}
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static void ppc4xx_dma_reset(void *opaque)
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{
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PPC4xxDmaState *dma = opaque;
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int dma_base = dma->base;
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memset(dma, 0, sizeof(*dma));
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dma->base = dma_base;
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}
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void ppc4xx_dma_init(CPUPPCState *env, int dcr_base)
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{
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PPC4xxDmaState *dma;
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int i;
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dma = g_malloc0(sizeof(*dma));
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dma->base = dcr_base;
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qemu_register_reset(&ppc4xx_dma_reset, dma);
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for (i = 0; i < 4; i++) {
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ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CR,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CT,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAH,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAL,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAH,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAL,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGH,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGL,
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dma, &dcr_read_dma, &dcr_write_dma);
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}
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ppc_dcr_register(env, dcr_base + DMA0_SR,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, dcr_base + DMA0_SGC,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, dcr_base + DMA0_SLP,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, dcr_base + DMA0_POL,
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dma, &dcr_read_dma, &dcr_write_dma);
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}
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/*****************************************************************************/
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/* PCI Express controller */
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/* FIXME: This is not complete and does not work, only implemented partially
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@ -505,6 +505,9 @@ static void sam460ex_init(MachineState *machine)
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/* MAL */
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ppc4xx_mal_init(env, 4, 16, &uic[2][3]);
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/* DMA */
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ppc4xx_dma_init(env, 0x200);
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/* 256K of L2 cache as memory */
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ppc4xx_l2sram_init(env);
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/* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */
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