OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

Target specific usermode cleanup 

Disable various target specific code that is only relevant to system emulation.

Signed-off-by: Paul Brook <paul@codesourcery.com>
This commit is contained in:
Paul Brook 2010-03-01 04:11:28 +00:00
parent 4fcc562bff
commit 3c7b48b74c
8 changed files with 41 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target-microblaze/cpu.h
View File

@ -327,6 +327,8 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
*flags = env->iflags & IFLAGS_TB_MASK;
}
#if !defined(CONFIG_USER_ONLY)
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int is_asi, int size);
#endif
#endif

2
target-microblaze/op_helper.c
View File

@ -245,7 +245,6 @@ void helper_mmu_write(uint32_t rn, uint32_t v)
{
mmu_write(env, rn, v);
}
#endif
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int is_asi, int size)
@ -282,3 +281,4 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
}
env = saved_env;
}
#endif

11
target-mips/cpu.h
View File

@ -36,6 +36,7 @@ struct r4k_tlb_t {
target_ulong PFN[2];
};
#if !defined(CONFIG_USER_ONLY)
typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
struct CPUMIPSTLBContext {
uint32_t nb_tlb;
@ -51,6 +52,7 @@ struct CPUMIPSTLBContext {
} r4k;
} mmu;
};
#endif
typedef union fpr_t fpr_t;
union fpr_t {
@ -468,13 +470,16 @@ struct CPUMIPSState {
CPU_COMMON
CPUMIPSMVPContext *mvp;
#if !defined(CONFIG_USER_ONLY)
CPUMIPSTLBContext *tlb;
#endif
const mips_def_t *cpu_model;
void *irq[8];
struct QEMUTimer *timer; /* Internal timer */
};
#if !defined(CONFIG_USER_ONLY)
int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
target_ulong address, int rw, int access_type);
int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
@ -485,10 +490,12 @@ void r4k_helper_tlbwi (void);
void r4k_helper_tlbwr (void);
void r4k_helper_tlbp (void);
void r4k_helper_tlbr (void);
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int unused, int size);
#endif
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
#define cpu_init cpu_mips_init
#define cpu_exec cpu_mips_exec
@ -598,9 +605,11 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu);
#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
void do_interrupt (CPUState *env);
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,
int rw);
#endif
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{

5
target-mips/helper.c
View File

@ -34,6 +34,8 @@ enum {
TLBRET_MATCH = 0
};
#if !defined(CONFIG_USER_ONLY)
/* no MMU emulation */
int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
target_ulong address, int rw, int access_type)
@ -98,7 +100,6 @@ int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
return TLBRET_NOMATCH;
}
#if !defined(CONFIG_USER_ONLY)
static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
int *prot, target_ulong address,
int rw, int access_type)
@ -599,6 +600,7 @@ void do_interrupt (CPUState *env)
env->exception_index = EXCP_NONE;
}
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
{
r4k_tlb_t *tlb;
@ -652,3 +654,4 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
}
}
}
#endif

6
target-ppc/cpu.h
View File

@ -332,6 +332,7 @@ union ppc_avr_t {
uint64_t u64[2];
};
#if !defined(CONFIG_USER_ONLY)
/* Software TLB cache */
typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
struct ppc6xx_tlb_t {
@ -354,6 +355,7 @@ union ppc_tlb_t {
ppc6xx_tlb_t tlb6;
ppcemb_tlb_t tlbe;
};
#endif
typedef struct ppc_slb_t ppc_slb_t;
struct ppc_slb_t {
@ -699,6 +701,7 @@ struct CPUPPCState {
int (*osi_call)(struct CPUPPCState *env);
};
#if !defined(CONFIG_USER_ONLY)
/* Context used internally during MMU translations */
typedef struct mmu_ctx_t mmu_ctx_t;
struct mmu_ctx_t {
@ -710,6 +713,7 @@ struct mmu_ctx_t {
int key; /* Access key */
int nx; /* Non-execute area */
};
#endif
/*****************************************************************************/
CPUPPCState *cpu_ppc_init (const char *cpu_model);
@ -724,8 +728,10 @@ int cpu_ppc_signal_handler (int host_signum, void *pinfo,
int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu);
#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
#if !defined(CONFIG_USER_ONLY)
int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
int rw, int access_type);
#endif
void do_interrupt (CPUPPCState *env);
void ppc_hw_interrupt (CPUPPCState *env);

2
target-sh4/cpu.h
View File

@ -169,9 +169,11 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
void do_interrupt(CPUSH4State * env);
void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
#if !defined(CONFIG_USER_ONLY)
void cpu_sh4_invalidate_tlb(CPUSH4State *s);
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
uint32_t mem_value);
#endif
int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);

2
target-sparc/cpu.h
View File

@ -550,8 +550,10 @@ static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
#endif
/* cpu-exec.c */
#if !defined(CONFIG_USER_ONLY)
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int is_asi, int size);
#endif
int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
#define cpu_init cpu_sparc_init

15
target-sparc/op_helper.c
View File

@ -47,6 +47,11 @@
#endif
#endif
#if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
int is_asi, int size);
#endif
#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
// Calculates TSB pointer value for fault page size 8k or 64k
static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
@ -3707,9 +3712,10 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
env = saved_env;
}
#endif
#endif /* !CONFIG_USER_ONLY */
#ifndef TARGET_SPARC64
#if !defined(CONFIG_USER_ONLY)
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int is_asi, int size)
{
@ -3770,9 +3776,15 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
env = saved_env;
}
#endif
#else
#if defined(CONFIG_USER_ONLY)
static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
int is_asi, int size)
#else
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int is_asi, int size)
#endif
{
CPUState *saved_env;
@ -3795,6 +3807,7 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
}
#endif
#ifdef TARGET_SPARC64
void helper_tick_set_count(void *opaque, uint64_t count)
{