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hw/intc: add implementation of GICD_IIDR to Arm GIC

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a66a24585f (hw/intc/arm_gic: Implement read of GICC_IIDR) implemented
this for the CPU interface register. The fact we don't implement it
shows up when running Xen with -d guest_error which is definitely
wrong because the guest is perfectly entitled to read it.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alex Bennée 2022-11-21 11:45:13 +00:00 committed by Peter Maydell
parent 69e7e60d01
commit 3d5af538a4
1 changed files with 11 additions and 1 deletions
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12
hw/intc/arm_gic.c
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@ -973,8 +973,18 @@ static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
/* GICD_TYPER byte 1 */
return (s->security_extn << 2);
}
if (offset < 0x08)
if (offset == 8) {
/* GICD_IIDR byte 0 */
return 0x3b; /* Arm JEP106 identity */
}
if (offset == 9) {
/* GICD_IIDR byte 1 */
return 0x04; /* Arm JEP106 identity */
}
if (offset < 0x0c) {
/* All other bytes in this range are RAZ */
return 0;
}
if (offset >= 0x80) {
/* Interrupt Group Registers: these RAZ/WI if this is an NS
* access to a GIC with the security extensions, or if the GIC