target/arm: Add SME enablement checks
These functions will be used to verify that the cpu is in the correct state for a given instruction. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1216,6 +1216,40 @@ static bool sme_access_check(DisasContext *s)
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return true;
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}
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/* This function corresponds to CheckSMEEnabled. */
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bool sme_enabled_check(DisasContext *s)
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{
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/*
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* Note that unlike sve_excp_el, we have not constrained sme_excp_el
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* to be zero when fp_excp_el has priority. This is because we need
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* sme_excp_el by itself for cpregs access checks.
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*/
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if (!s->fp_excp_el || s->sme_excp_el < s->fp_excp_el) {
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s->fp_access_checked = true;
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return sme_access_check(s);
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}
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return fp_access_check_only(s);
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}
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/* Common subroutine for CheckSMEAnd*Enabled. */
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bool sme_enabled_check_with_svcr(DisasContext *s, unsigned req)
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{
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if (!sme_enabled_check(s)) {
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return false;
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}
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if (FIELD_EX64(req, SVCR, SM) && !s->pstate_sm) {
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
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syn_smetrap(SME_ET_NotStreaming, false));
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return false;
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}
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if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) {
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
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syn_smetrap(SME_ET_InactiveZA, false));
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return false;
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}
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return true;
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}
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/*
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* This utility function is for doing register extension with an
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* optional shift. You will likely want to pass a temporary for the
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@ -29,6 +29,27 @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
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bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
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unsigned int imms, unsigned int immr);
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bool sve_access_check(DisasContext *s);
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bool sme_enabled_check(DisasContext *s);
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bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
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/* This function corresponds to CheckStreamingSVEEnabled. */
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static inline bool sme_sm_enabled_check(DisasContext *s)
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{
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return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK);
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}
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/* This function corresponds to CheckSMEAndZAEnabled. */
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static inline bool sme_za_enabled_check(DisasContext *s)
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{
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return sme_enabled_check_with_svcr(s, R_SVCR_ZA_MASK);
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}
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/* Note that this function corresponds to CheckStreamingSVEAndZAEnabled. */
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static inline bool sme_smza_enabled_check(DisasContext *s)
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{
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return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
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}
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TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
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TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
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bool tag_checked, int log2_size);
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