e2k: add more cpu models and set idr.mdl
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@ -204,13 +204,20 @@ const char *cpu_get_model(uint32_t eflags)
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/* TODO: can't check for EM_E2K_OLD flags because e_machine isn't saved anywhere... */
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switch(machine) {
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case E2K_MACH_EV2: name = "e2c+"; break;
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case E2K_MACH_EV3: name = "e2s"; break;
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case E2K_MACH_EV1: name = "elbrus-v1"; break;
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case E2K_MACH_EV2: name = "elbrus-v2"; break;
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case E2K_MACH_EV3: name = "elbrus-v3"; break;
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case E2K_MACH_1CPLUS:
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case E2K_MACH_8C:
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case E2K_MACH_EV4: name = "e8c"; break;
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case E2K_MACH_EV5: name = "e8c2"; break;
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case E2K_MACH_EV6: name = "e16c"; break;
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case E2K_MACH_EV4: name = "elbrus-v4"; break;
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case E2K_MACH_EV5: name = "elbrus-v5"; break;
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case E2K_MACH_12C:
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case E2K_MACH_16C:
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case E2K_MACH_2C3:
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case E2K_MACH_EV6: name = "elbrus-v6"; break;
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case E2K_MACH_48C:
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case E2K_MACH_8V7:
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case E2K_MACH_EV7: name = "elbrus-v7"; break;
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}
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return name;
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@ -17,11 +17,21 @@
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#define E2K_MACH_EV4 4
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#define E2K_MACH_EV5 5
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#define E2K_MACH_EV6 6
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#define E2K_MACH_EV7 7
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/* elbrus-v4 based processors */
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#define E2K_MACH_8C 19
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#define E2K_MACH_1CPLUS 20
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/* elbrus-v6 based processors */
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#define E2K_MACH_12C 21
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#define E2K_MACH_16C 22
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#define E2K_MACH_2C3 23
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/* elbrus-v7 based processors */
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#define E2K_MACH_48C 24
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#define E2K_MACH_8V7 25
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const char *cpu_get_model(uint32_t eflags);
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#endif /* E2K_TARGET_ELF_H */
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@ -61,9 +61,6 @@ static void e2k_cpu_reset(DeviceState *dev)
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e2k_update_fp_status(env);
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e2k_update_fx_status(env);
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// FIXME: testing
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env->idr = 0x3a207; /* mimic 8c */
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// FIXME: correct values
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env->psp.base = 0x810000;
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env->psp.size = 0x100000;
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@ -100,37 +97,58 @@ static void e2k_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
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/* https://www.altlinux.org/Модели_процессоров_Эльбрус */
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#define DEFAULT_CPU_MODEL "e8c"
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#define MDL_E3M 0 /* Elbrus */
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#define MDL_ES 1 /* Elbrus-S */
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#define MDL_E3S 2 /* Elbrus-3S */
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#define MDL_E2S 3 /* Elbrus-4C */
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#define MDL_ES2 4 /* Elbrus-2C+ */
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#define MDL_RESERVED 5 /* unknown "reserved" processor */
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#define MDL_ES2_NO_DSP 6 /* Elbrus-2CM */
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#define MDL_E8C 7 /* Elbrus-8C */
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#define MDL_E1CP 8 /* Elbrus-1C+ */
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#define MDL_E8C2 9 /* Elbrus-8C2 */
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#define MDL_E12C 10 /* Elbrus-12C */
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#define MDL_E16C 11 /* Elbrus-16C */
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#define MDL_E2C3 12 /* Elbrus-2C3 */
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#define MDL_E48C 13 /* Elbrus-48C FIXME: assumption */
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#define MDL_E8V7 14 /* Elbrus-8v7 FIXME: assumption */
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#define CPU_MODEL(ISET, NAME, GDB_ARCH, IDR, CANON) \
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{ \
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.name = NAME, \
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.canonical_name = CANON, \
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.gdb_arch = GDB_ARCH, \
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.isa_version = ISET, \
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.idr = IDR, \
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}
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static const struct e2k_def_t e2k_defs[] = {
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{
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.name = "e2cplus", /* however it may work better */
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.canonical_name = "MCST Elbrus 2C+ (Monocube)",
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.gdb_arch = "elbrus-v2",
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.isa_version = 2,
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},
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{
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.name = "e2s",
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.canonical_name = "MCST Elbrus 4C",
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.gdb_arch = "elbrus-v3",
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.isa_version = 3,
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},
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{
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.name = "e8c", /* default choice for system */
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.canonical_name = "MCST Elbrus 8C",
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.gdb_arch = "elbrus-8c",
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.isa_version = 4,
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},
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{
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.name = "e8c2",
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.canonical_name = "MCST Elbrus 8CB",
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.gdb_arch = "elbrus-v5",
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.isa_version = 5,
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},
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{
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.name = "e16c",
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.canonical_name = "MCST Elbrus 16C",
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.gdb_arch = "elbrus-v6",
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.isa_version = 6,
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},
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CPU_MODEL(1, "elbrus-v1", "elbrus-v1", MDL_E3M, "MCST Elbrus"),
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CPU_MODEL(2, "elbrus-v2", "elbrus-v2", MDL_ES, "MCST Elbrus-S"),
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CPU_MODEL(3, "elbrus-v3", "elbrus-v3", MDL_E2S, "MCST Elbrus-4C"),
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CPU_MODEL(4, "elbrus-v4", "elbrus-v4", MDL_E8C, "MCST Elbrus-8C"),
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CPU_MODEL(5, "elbrus-v5", "elbrus-v5", MDL_E8C2, "MCST Elbrus-8C2"),
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CPU_MODEL(6, "elbrus-v6", "elbrus-v6", MDL_E16C, "MCST Elbrus-16C"),
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CPU_MODEL(7, "elbrus-v7", "elbrus-v7", MDL_E48C, "MCST Elbrus-48C"),
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CPU_MODEL(1, "generic", "elbrus-v1", MDL_E3M, "MCST Elbrus"),
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CPU_MODEL(1, "elbrus", "elbrus-v1", MDL_E3M, "MCST Elbrus"),
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CPU_MODEL(1, "e3m", "elbrus-v1", MDL_E3M, "MCST Elbrus-3M1"),
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CPU_MODEL(2, "elbrus-s", "elbrus-v2", MDL_ES, "MCST Elbrus-S"),
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CPU_MODEL(2, "e3s", "elbrus-v2", MDL_E3S, "MCST Elbrus-3S"),
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CPU_MODEL(2, "es2", "elbrus-v2", MDL_ES2, "MCST Elbrus-2C+ (Monocube)"),
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CPU_MODEL(2, "e2cplus", "elbrus-v2", MDL_ES2, "MCST Elbrus-2C+ (Monocube)"),
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CPU_MODEL(2, "e2cm", "elbrus-v2", MDL_ES2_NO_DSP, "MCST Elbrus-2CM"),
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CPU_MODEL(3, "e2s", "elbrus-v3", MDL_E2S, "MCST Elbrus-4C"),
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CPU_MODEL(3, "e4c", "elbrus-v3", MDL_E2S, "MCST Elbrus-4C"),
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CPU_MODEL(4, "e8c", "elbrus-8c", MDL_E8C, "MCST Elbrus-8C"),
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CPU_MODEL(4, "e1cplus", "elbrus-1c+", MDL_E1CP, "MCST Elbrus-1C+"),
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CPU_MODEL(5, "e8c2", "elbrus-v5", MDL_E8C2, "MCST Elbrus-8C2"),
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CPU_MODEL(6, "e16c", "elbrus-16c", MDL_E16C, "MCST Elbrus-16C"),
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CPU_MODEL(6, "e12c", "elbrus-12c", MDL_E12C, "MCST Elbrus-12C"),
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CPU_MODEL(6, "e2c3", "elbrus-2c3", MDL_E2C3, "MCST Elbrus-2C3"),
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CPU_MODEL(7, "e48c", "elbrus-v7", MDL_E48C, "MCST Elbrus-48C"),
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CPU_MODEL(7, "e8v7", "elbrus-v7", MDL_E8V7, "MCST Elbrus-8v7"),
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};
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static void e2k_cpu_set_pc(CPUState *cs, vaddr value)
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@ -207,6 +225,7 @@ static void e2k_cpu_realizefn(DeviceState *dev, Error **errp)
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E2KCPU *cpu = E2K_CPU(dev);
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CPUE2KState *env = &cpu->env;
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env->idr = env->def.idr;
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env->version = env->def.isa_version;
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cpu_exec_realizefn(cs, &local_err);
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@ -336,7 +355,7 @@ void e2k_cpu_list(void)
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size_t len = 0;
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for (i = 0; i < ARRAY_SIZE(e2k_defs); i++) {
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qemu_printf("%6s (%-30s) ISA version: v%d\n",
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qemu_printf("%12s (%-30s) ISA version: v%d\n",
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e2k_defs[i].name,
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e2k_defs[i].canonical_name,
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e2k_defs[i].isa_version
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@ -400,6 +400,7 @@ struct e2k_def_t {
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const char *canonical_name;
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const char *gdb_arch;
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uint32_t isa_version;
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uint64_t idr;
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};
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typedef struct {
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@ -837,7 +838,6 @@ typedef struct CPUArchState {
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uint32_t cuir;
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/* System Register */
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uint64_t osr0;
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uint64_t idr;
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uint64_t core_mode;
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/* Packed Floating Point Flag Register (PFPFR) */
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@ -893,6 +893,7 @@ typedef struct CPUArchState {
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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uint64_t idr;
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/* ISA version */
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uint32_t version;
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/* Force alop to preserve the destination register before writing to it.
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