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target-lm32: add breakpoint/watchpoint support

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This patch adds in-target breakpoint and watchpoint support.

Signed-off-by: Michael Walle <michael@walle.cc>
This commit is contained in:
Michael Walle 2013-09-18 19:10:45 +02:00
parent 34f4aa83f9
commit 3dd3a2b965
7 changed files with 179 additions and 8 deletions
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2
target-lm32/TODO
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@ -1,3 +1 @@
* disassembler (lm32-dis.c)
* linux-user emulation
* native bp/wp emulation (?)

1
target-lm32/cpu.c
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@ -153,6 +153,7 @@ static void lm32_cpu_initfn(Object *obj)
if (tcg_enabled() && !tcg_initialized) {
tcg_initialized = true;
lm32_translate_init();
cpu_set_debug_excp_handler(lm32_debug_excp_handler);
}
}

27
target-lm32/cpu.h
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@ -163,8 +163,11 @@ struct CPULM32State {
/* debug registers */
uint32_t dc; /* debug control */
uint32_t bp[4]; /* breakpoint addresses */
uint32_t wp[4]; /* watchpoint addresses */
uint32_t bp[4]; /* breakpoints */
uint32_t wp[4]; /* watchpoints */
CPUBreakpoint * cpu_breakpoint[4];
CPUWatchpoint * cpu_watchpoint[4];
CPU_COMMON
@ -181,6 +184,19 @@ struct CPULM32State {
};
typedef enum {
LM32_WP_DISABLED = 0,
LM32_WP_READ,
LM32_WP_WRITE,
LM32_WP_READ_WRITE,
} lm32_wp_t;
static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx)
{
assert(idx < 4);
return (dc >> (idx+1)*2) & 0x3;
}
#include "cpu-qom.h"
LM32CPU *cpu_lm32_init(const char *cpu_model);
@ -193,6 +209,13 @@ int cpu_lm32_signal_handler(int host_signum, void *pinfo,
void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf);
void lm32_translate_init(void);
void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
void QEMU_NORETURN raise_exception(CPULM32State *env, int index);
void lm32_debug_excp_handler(CPULM32State *env);
void lm32_breakpoint_insert(CPULM32State *env, int index, target_ulong address);
void lm32_breakpoint_remove(CPULM32State *env, int index);
void lm32_watchpoint_insert(CPULM32State *env, int index, target_ulong address,
lm32_wp_t wp_type);
void lm32_watchpoint_remove(CPULM32State *env, int index);
static inline CPULM32State *cpu_init(const char *cpu_model)
{

90
target-lm32/helper.c
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@ -49,6 +49,96 @@ hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
}
void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
{
cpu_breakpoint_insert(env, address, BP_CPU, &env->cpu_breakpoint[idx]);
}
void lm32_breakpoint_remove(CPULM32State *env, int idx)
{
if (!env->cpu_breakpoint[idx]) {
return;
}
cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[idx]);
env->cpu_breakpoint[idx] = NULL;
}
void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
lm32_wp_t wp_type)
{
int flags = 0;
switch (wp_type) {
case LM32_WP_DISABLED:
/* nothing to to */
break;
case LM32_WP_READ:
flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ;
break;
case LM32_WP_WRITE:
flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE;
break;
case LM32_WP_READ_WRITE:
flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS;
break;
}
if (flags != 0) {
cpu_watchpoint_insert(env, address, 1, flags,
&env->cpu_watchpoint[idx]);
}
}
void lm32_watchpoint_remove(CPULM32State *env, int idx)
{
if (!env->cpu_watchpoint[idx]) {
return;
}
cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[idx]);
env->cpu_watchpoint[idx] = NULL;
}
static bool check_watchpoints(CPULM32State *env)
{
LM32CPU *cpu = lm32_env_get_cpu(env);
int i;
for (i = 0; i < cpu->num_watchpoints; i++) {
if (env->cpu_watchpoint[i] &&
env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
return true;
}
}
return false;
}
void lm32_debug_excp_handler(CPULM32State *env)
{
CPUBreakpoint *bp;
if (env->watchpoint_hit) {
if (env->watchpoint_hit->flags & BP_CPU) {
env->watchpoint_hit = NULL;
if (check_watchpoints(env)) {
raise_exception(env, EXCP_WATCHPOINT);
} else {
cpu_resume_from_signal(env, NULL);
}
}
} else {
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
if (bp->pc == env->pc) {
if (bp->flags & BP_CPU) {
raise_exception(env, EXCP_BREAKPOINT);
}
break;
}
}
}
}
void lm32_cpu_do_interrupt(CPUState *cs)
{
LM32CPU *cpu = LM32_CPU(cs);

3
target-lm32/helper.h
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@ -2,6 +2,9 @@
DEF_HELPER_2(raise_exception, void, env, i32)
DEF_HELPER_1(hlt, void, env)
DEF_HELPER_3(wcsr_bp, void, env, i32, i32)
DEF_HELPER_3(wcsr_wp, void, env, i32, i32)
DEF_HELPER_2(wcsr_dc, void, env, i32)
DEF_HELPER_2(wcsr_im, void, env, i32)
DEF_HELPER_2(wcsr_ip, void, env, i32)
DEF_HELPER_2(wcsr_jtx, void, env, i32)

58
target-lm32/op_helper.c
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@ -19,12 +19,17 @@
#define SHIFT 3
#include "exec/softmmu_template.h"
void HELPER(raise_exception)(CPULM32State *env, uint32_t index)
void raise_exception(CPULM32State *env, int index)
{
env->exception_index = index;
cpu_loop_exit(env);
}
void HELPER(raise_exception)(CPULM32State *env, uint32_t index)
{
raise_exception(env, index);
}
void HELPER(hlt)(CPULM32State *env)
{
CPUState *cs = CPU(lm32_env_get_cpu(env));
@ -34,6 +39,57 @@ void HELPER(hlt)(CPULM32State *env)
cpu_loop_exit(env);
}
void HELPER(wcsr_bp)(CPULM32State *env, uint32_t bp, uint32_t idx)
{
uint32_t addr = bp & ~1;
assert(idx < 4);
env->bp[idx] = bp;
lm32_breakpoint_remove(env, idx);
if (bp & 1) {
lm32_breakpoint_insert(env, idx, addr);
}
}
void HELPER(wcsr_wp)(CPULM32State *env, uint32_t wp, uint32_t idx)
{
lm32_wp_t wp_type;
assert(idx < 4);
env->wp[idx] = wp;
wp_type = lm32_wp_type(env->dc, idx);
lm32_watchpoint_remove(env, idx);
if (wp_type != LM32_WP_DISABLED) {
lm32_watchpoint_insert(env, idx, wp, wp_type);
}
}
void HELPER(wcsr_dc)(CPULM32State *env, uint32_t dc)
{
uint32_t old_dc;
int i;
lm32_wp_t old_type;
lm32_wp_t new_type;
old_dc = env->dc;
env->dc = dc;
for (i = 0; i < 4; i++) {
old_type = lm32_wp_type(old_dc, i);
new_type = lm32_wp_type(dc, i);
if (old_type != new_type) {
lm32_watchpoint_remove(env, i);
if (new_type != LM32_WP_DISABLED) {
lm32_watchpoint_insert(env, i, env->wp[i], new_type);
}
}
}
}
void HELPER(wcsr_im)(CPULM32State *env, uint32_t im)
{
lm32_pic_set_im(env->pic_state, im);

6
target-lm32/translate.c
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@ -876,7 +876,7 @@ static void dec_wcsr(DisasContext *dc)
gen_helper_wcsr_jrx(cpu_env, cpu_R[dc->r1]);
break;
case CSR_DC:
tcg_gen_mov_tl(cpu_dc, cpu_R[dc->r1]);
gen_helper_wcsr_dc(cpu_env, cpu_R[dc->r1]);
break;
case CSR_BP0:
case CSR_BP1:
@ -888,7 +888,7 @@ static void dec_wcsr(DisasContext *dc)
"breakpoint #%i is not available\n", no);
break;
}
tcg_gen_mov_tl(cpu_bp[no], cpu_R[dc->r1]);
gen_helper_wcsr_bp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
break;
case CSR_WP0:
case CSR_WP1:
@ -900,7 +900,7 @@ static void dec_wcsr(DisasContext *dc)
"watchpoint #%i is not available\n", no);
break;
}
tcg_gen_mov_tl(cpu_wp[no], cpu_R[dc->r1]);
gen_helper_wcsr_wp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
break;
case CSR_CC:
case CSR_CFG: