more generic i8259 support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1487 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
73133662c6
commit
3de388f676
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@ -360,8 +360,8 @@ VL_OBJS+= mc146818rtc.o serial.o i8259.o i8254.o fdc.o m48t59.o
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VL_OBJS+= ppc_prep.o ppc_chrp.o cuda.o adb.o openpic.o heathrow_pic.o mixeng.o
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endif
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ifeq ($(TARGET_ARCH), mips)
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VL_OBJS+= mips.o mips_r4k.o dma.o vga.o serial.o ne2000.o #ide.o pckbd.o
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VL_OBJS+= #i8259.o i8254.o fdc.o m48t59.o
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VL_OBJS+= mips_r4k.o dma.o vga.o serial.o ne2000.o i8259.o
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#VL_OBJS+= #ide.o pckbd.o i8254.o fdc.o m48t59.o
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endif
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ifeq ($(TARGET_BASE_ARCH), sparc)
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ifeq ($(TARGET_ARCH), sparc64)
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145
hw/i8259.c
145
hw/i8259.c
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@ -46,10 +46,16 @@ typedef struct PicState {
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uint8_t init4; /* true if 4 byte init */
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uint8_t elcr; /* PIIX edge/trigger selection*/
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uint8_t elcr_mask;
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PicState2 *pics_state;
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} PicState;
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/* 0 is master pic, 1 is slave pic */
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static PicState pics[2];
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struct PicState2 {
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/* 0 is master pic, 1 is slave pic */
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/* XXX: better separation between the two pics */
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PicState pics[2];
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IRQRequestFunc *irq_request;
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void *irq_request_opaque;
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};
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#if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
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static int irq_level[16];
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@ -110,7 +116,7 @@ static int pic_get_irq(PicState *s)
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master, the IRQ coming from the slave is not taken into account
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for the priority computation. */
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mask = s->isr;
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if (s->special_fully_nested_mode && s == &pics[0])
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if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
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mask &= ~(1 << 2);
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cur_priority = get_priority(s, mask);
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if (priority < cur_priority) {
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@ -123,32 +129,34 @@ static int pic_get_irq(PicState *s)
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/* raise irq to CPU if necessary. must be called every time the active
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irq may change */
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static void pic_update_irq(void)
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/* XXX: should not export it, but it is needed for an APIC kludge */
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void pic_update_irq(PicState2 *s)
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{
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int irq2, irq;
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/* first look at slave pic */
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irq2 = pic_get_irq(&pics[1]);
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irq2 = pic_get_irq(&s->pics[1]);
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if (irq2 >= 0) {
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/* if irq request by slave pic, signal master PIC */
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pic_set_irq1(&pics[0], 2, 1);
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pic_set_irq1(&pics[0], 2, 0);
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pic_set_irq1(&s->pics[0], 2, 1);
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pic_set_irq1(&s->pics[0], 2, 0);
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}
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/* look at requested irq */
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irq = pic_get_irq(&pics[0]);
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irq = pic_get_irq(&s->pics[0]);
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if (irq >= 0) {
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#if defined(DEBUG_PIC)
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{
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int i;
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for(i = 0; i < 2; i++) {
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printf("pic%d: imr=%x irr=%x padd=%d\n",
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i, pics[i].imr, pics[i].irr, pics[i].priority_add);
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i, s->pics[i].imr, s->pics[i].irr,
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s->pics[i].priority_add);
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}
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}
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printf("pic: cpu_interrupt\n");
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#endif
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
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s->irq_request(s->irq_request_opaque, 1);
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}
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}
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@ -156,8 +164,10 @@ static void pic_update_irq(void)
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int64_t irq_time[16];
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#endif
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void pic_set_irq(int irq, int level)
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void pic_set_irq_new(void *opaque, int irq, int level)
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{
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PicState2 *s = opaque;
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#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
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if (level != irq_level[irq]) {
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#if defined(DEBUG_PIC)
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@ -175,14 +185,14 @@ void pic_set_irq(int irq, int level)
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irq_time[irq] = qemu_get_clock(vm_clock);
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}
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#endif
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pic_set_irq1(&pics[irq >> 3], irq & 7, level);
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pic_update_irq();
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pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
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pic_update_irq(s);
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}
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/* this function should be used to have the controller context */
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void pic_set_irq_new(void *opaque, int irq, int level)
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/* obsolete function */
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void pic_set_irq(int irq, int level)
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{
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pic_set_irq(irq, level);
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pic_set_irq_new(isa_pic, irq, level);
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}
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/* acknowledge interrupt 'irq' */
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@ -199,43 +209,32 @@ static inline void pic_intack(PicState *s, int irq)
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s->irr &= ~(1 << irq);
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}
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int cpu_get_pic_interrupt(CPUState *env)
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int pic_read_irq(PicState2 *s)
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{
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int irq, irq2, intno;
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#ifdef TARGET_X86_64
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intno = apic_get_interrupt(env);
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if (intno >= 0) {
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/* set irq request if a PIC irq is still pending */
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/* XXX: improve that */
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pic_update_irq();
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return intno;
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}
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#endif
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/* read the irq from the PIC */
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irq = pic_get_irq(&pics[0]);
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irq = pic_get_irq(&s->pics[0]);
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if (irq >= 0) {
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pic_intack(&pics[0], irq);
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pic_intack(&s->pics[0], irq);
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if (irq == 2) {
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irq2 = pic_get_irq(&pics[1]);
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irq2 = pic_get_irq(&s->pics[1]);
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if (irq2 >= 0) {
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pic_intack(&pics[1], irq2);
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pic_intack(&s->pics[1], irq2);
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} else {
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/* spurious IRQ on slave controller */
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irq2 = 7;
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}
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intno = pics[1].irq_base + irq2;
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intno = s->pics[1].irq_base + irq2;
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irq = irq2 + 8;
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} else {
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intno = pics[0].irq_base + irq;
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intno = s->pics[0].irq_base + irq;
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}
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} else {
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/* spurious IRQ on host controller */
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irq = 7;
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intno = pics[0].irq_base + irq;
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intno = s->pics[0].irq_base + irq;
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}
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pic_update_irq();
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pic_update_irq(s);
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#ifdef DEBUG_IRQ_LATENCY
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printf("IRQ%d latency=%0.3fus\n",
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@ -251,11 +250,22 @@ int cpu_get_pic_interrupt(CPUState *env)
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static void pic_reset(void *opaque)
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{
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PicState *s = opaque;
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int tmp;
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tmp = s->elcr_mask;
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memset(s, 0, sizeof(PicState));
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s->elcr_mask = tmp;
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s->last_irr = 0;
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s->irr = 0;
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s->imr = 0;
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s->isr = 0;
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s->priority_add = 0;
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s->irq_base = 0;
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s->read_reg_select = 0;
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s->poll = 0;
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s->special_mask = 0;
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s->init_state = 0;
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s->auto_eoi = 0;
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s->rotate_on_auto_eoi = 0;
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s->special_fully_nested_mode = 0;
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s->init4 = 0;
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s->elcr = 0;
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}
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static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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@ -272,8 +282,7 @@ static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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/* init */
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pic_reset(s);
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/* deassert a pending interrupt */
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cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
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s->pics_state->irq_request(s->pics_state->irq_request_opaque, 0);
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s->init_state = 1;
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s->init4 = val & 1;
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if (val & 0x02)
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@ -302,23 +311,23 @@ static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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s->isr &= ~(1 << irq);
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if (cmd == 5)
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s->priority_add = (irq + 1) & 7;
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pic_update_irq();
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pic_update_irq(s->pics_state);
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}
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break;
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case 3:
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irq = val & 7;
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s->isr &= ~(1 << irq);
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pic_update_irq();
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pic_update_irq(s->pics_state);
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break;
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case 6:
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s->priority_add = (val + 1) & 7;
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pic_update_irq();
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pic_update_irq(s->pics_state);
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break;
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case 7:
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irq = val & 7;
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s->isr &= ~(1 << irq);
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s->priority_add = (irq + 1) & 7;
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pic_update_irq();
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pic_update_irq(s->pics_state);
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break;
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default:
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/* no operation */
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@ -330,7 +339,7 @@ static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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case 0:
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/* normal mode */
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s->imr = val;
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pic_update_irq();
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pic_update_irq(s->pics_state);
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break;
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case 1:
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s->irq_base = val & 0xf8;
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@ -359,16 +368,16 @@ static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
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ret = pic_get_irq(s);
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if (ret >= 0) {
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if (addr1 >> 7) {
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pics[0].isr &= ~(1 << 2);
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pics[0].irr &= ~(1 << 2);
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s->pics_state->pics[0].isr &= ~(1 << 2);
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s->pics_state->pics[0].irr &= ~(1 << 2);
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}
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s->irr &= ~(1 << ret);
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s->isr &= ~(1 << ret);
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if (addr1 >> 7 || ret != 2)
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pic_update_irq();
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pic_update_irq(s->pics_state);
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} else {
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ret = 0x07;
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pic_update_irq();
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pic_update_irq(s->pics_state);
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}
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return ret;
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@ -402,15 +411,16 @@ static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
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}
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/* memory mapped interrupt status */
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uint32_t pic_intack_read(CPUState *env)
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/* XXX: may be the same than pic_read_irq() */
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uint32_t pic_intack_read(PicState2 *s)
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{
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int ret;
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ret = pic_poll_read(&pics[0], 0x00);
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ret = pic_poll_read(&s->pics[0], 0x00);
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if (ret == 2)
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ret = pic_poll_read(&pics[1], 0x80) + 8;
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ret = pic_poll_read(&s->pics[1], 0x80) + 8;
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/* Prepare for ISR read */
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pics[0].read_reg_select = 1;
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s->pics[0].read_reg_select = 1;
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return ret;
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}
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@ -490,9 +500,12 @@ void pic_info(void)
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{
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int i;
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PicState *s;
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if (!isa_pic)
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return;
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for(i=0;i<2;i++) {
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s = &pics[i];
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s = &isa_pic->pics[i];
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term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
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i, s->irr, s->imr, s->isr, s->priority_add,
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s->irq_base, s->read_reg_select, s->elcr,
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@ -517,11 +530,19 @@ void irq_info(void)
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#endif
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}
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void pic_init(void)
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PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque)
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{
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pic_init1(0x20, 0x4d0, &pics[0]);
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pic_init1(0xa0, 0x4d1, &pics[1]);
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pics[0].elcr_mask = 0xf8;
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pics[1].elcr_mask = 0xde;
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PicState2 *s;
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s = qemu_mallocz(sizeof(PicState2));
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if (!s)
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return NULL;
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pic_init1(0x20, 0x4d0, &s->pics[0]);
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pic_init1(0xa0, 0x4d1, &s->pics[1]);
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s->pics[0].elcr_mask = 0xf8;
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s->pics[1].elcr_mask = 0xde;
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s->irq_request = irq_request;
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s->irq_request_opaque = irq_request_opaque;
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s->pics[0].pics_state = s;
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s->pics[1].pics_state = s;
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return s;
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}
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6
hw/ide.c
6
hw/ide.c
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@ -2008,7 +2008,7 @@ void isa_ide_init(int iobase, int iobase2, int irq,
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if (!ide_state)
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return;
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ide_init2(ide_state, hd0, hd1, pic_set_irq_new, NULL, irq);
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ide_init2(ide_state, hd0, hd1, pic_set_irq_new, isa_pic, irq);
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ide_init_ioport(ide_state, iobase, iobase2);
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}
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@ -2337,9 +2337,9 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table)
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PCI_ADDRESS_SPACE_IO, bmdma_map);
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ide_init2(&d->ide_if[0], hd_table[0], hd_table[1],
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pic_set_irq_new, NULL, 14);
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pic_set_irq_new, isa_pic, 14);
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ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
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pic_set_irq_new, NULL, 15);
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pic_set_irq_new, isa_pic, 15);
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ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
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ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
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}
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29
hw/pc.c
29
hw/pc.c
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@ -65,6 +65,33 @@ uint64_t cpu_get_tsc(CPUX86State *env)
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return qemu_get_clock(vm_clock);
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}
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUState *env)
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{
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int intno;
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#ifdef TARGET_X86_64
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intno = apic_get_interrupt(env);
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if (intno >= 0) {
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/* set irq request if a PIC irq is still pending */
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/* XXX: improve that */
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pic_update_irq(isa_pic);
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return intno;
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}
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#endif
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/* read the irq from the PIC */
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intno = pic_read_irq(isa_pic);
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return intno;
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}
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static void pic_irq_request(void *opaque, int level)
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{
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if (level)
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
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else
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cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
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}
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/* PC cmos mappings */
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#define REG_EQUIPMENT_BYTE 0x14
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@ -532,7 +559,7 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device,
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if (pci_enabled)
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apic_init(cpu_single_env);
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pic_init();
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isa_pic = pic_init(pic_irq_request, cpu_single_env);
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pit = pit_init(0x40, 0);
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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@ -213,6 +213,11 @@ static int vga_osi_call(CPUState *env)
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return 1; /* osi_call handled */
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}
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/* XXX: suppress that */
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static void pic_irq_request(void *opaque, int level)
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{
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}
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/* PowerPC CHRP hardware initialisation */
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static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename,
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@ -303,7 +308,7 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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pci_set_pic(pci_bus, set_irq, pic);
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/* XXX: suppress that */
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pic_init();
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pic_init(pic_irq_request, NULL);
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, 4, serial_hds[0]);
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@ -345,7 +350,7 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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pci_set_pic(pci_bus, set_irq, pic);
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/* XXX: suppress that */
|
||||
pic_init();
|
||||
pic_init(pic_irq_request, NULL);
|
||||
|
||||
/* XXX: use Mac Serial port */
|
||||
serial_init(0x3f8, 4, serial_hds[0]);
|
||||
|
|
|
|||
|
|
@ -96,6 +96,14 @@ static uint32_t speaker_ioport_read(void *opaque, uint32_t addr)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void pic_irq_request(void *opaque, int level)
|
||||
{
|
||||
if (level)
|
||||
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
|
||||
else
|
||||
cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
|
||||
/* PCI intack register */
|
||||
/* Read-only register (?) */
|
||||
static void _PPC_intack_write (void *opaque, target_phys_addr_t addr, uint32_t value)
|
||||
|
|
@ -108,7 +116,7 @@ static inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
|
|||
uint32_t retval = 0;
|
||||
|
||||
if (addr == 0xBFFFFFF0)
|
||||
retval = pic_intack_read(NULL);
|
||||
retval = pic_intack_read(isa_pic);
|
||||
// printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
|
||||
|
||||
return retval;
|
||||
|
|
@ -505,8 +513,6 @@ CPUReadMemoryFunc *PPC_prep_io_read[] = {
|
|||
&PPC_prep_io_readl,
|
||||
};
|
||||
|
||||
extern CPUPPCState *global_env;
|
||||
|
||||
#define NVRAM_SIZE 0x2000
|
||||
|
||||
/* PowerPC PREP hardware initialisation */
|
||||
|
|
@ -593,8 +599,7 @@ static void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
|
|||
vga_ram_size);
|
||||
rtc_init(0x70, 8);
|
||||
// openpic = openpic_init(0x00000000, 0xF0000000, 1);
|
||||
// pic_init(openpic);
|
||||
pic_init();
|
||||
isa_pic = pic_init(pic_irq_request, cpu_single_env);
|
||||
// pit = pit_init(0x40, 0);
|
||||
|
||||
serial_init(0x3f8, 4, serial_hds[0]);
|
||||
|
|
|
|||
1
vl.c
1
vl.c
|
|
@ -155,6 +155,7 @@ int win2k_install_hack = 0;
|
|||
/* x86 ISA bus support */
|
||||
|
||||
target_phys_addr_t isa_mem_base = 0;
|
||||
PicState2 *isa_pic;
|
||||
|
||||
uint32_t default_ioport_readb(void *opaque, uint32_t address)
|
||||
{
|
||||
|
|
|
|||
9
vl.h
9
vl.h
|
|
@ -469,6 +469,7 @@ typedef struct QEMUMachine {
|
|||
int qemu_register_machine(QEMUMachine *m);
|
||||
|
||||
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
|
||||
typedef void IRQRequestFunc(void *opaque, int level);
|
||||
|
||||
/* ISA bus */
|
||||
|
||||
|
|
@ -687,10 +688,14 @@ ParallelState *parallel_init(int base, int irq, CharDriverState *chr);
|
|||
|
||||
/* i8259.c */
|
||||
|
||||
typedef struct PicState2 PicState2;
|
||||
extern PicState2 *isa_pic;
|
||||
void pic_set_irq(int irq, int level);
|
||||
void pic_set_irq_new(void *opaque, int irq, int level);
|
||||
void pic_init(void);
|
||||
uint32_t pic_intack_read(CPUState *env);
|
||||
PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque);
|
||||
int pic_read_irq(PicState2 *s);
|
||||
void pic_update_irq(PicState2 *s);
|
||||
uint32_t pic_intack_read(PicState2 *s);
|
||||
void pic_info(void);
|
||||
void irq_info(void);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue