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target/ppc: implement vslq 

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-21-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst 2022-03-02 06:51:37 +01:00 committed by Cédric Le Goater
parent 0f05200782
commit 3e39edb688
2 changed files with 41 additions and 0 deletions
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1
target/ppc/insn32.decode
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@ -473,6 +473,7 @@ VSLB 000100 ..... ..... ..... 00100000100 @VX
VSLH 000100 ..... ..... ..... 00101000100 @VX
VSLW 000100 ..... ..... ..... 00110000100 @VX
VSLD 000100 ..... ..... ..... 10111000100 @VX
VSLQ 000100 ..... ..... ..... 00100000101 @VX
VSRB 000100 ..... ..... ..... 01000000100 @VX
VSRH 000100 ..... ..... ..... 01001000100 @VX

40
target/ppc/translate/vmx-impl.c.inc
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@ -834,6 +834,46 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
static bool trans_VSLQ(DisasContext *ctx, arg_VX *a)
{
TCGv_i64 hi, lo, t0, n, zero = tcg_constant_i64(0);
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
REQUIRE_VECTOR(ctx);
n = tcg_temp_new_i64();
hi = tcg_temp_new_i64();
lo = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
get_avr64(lo, a->vra, false);
get_avr64(hi, a->vra, true);
get_avr64(n, a->vrb, true);
tcg_gen_andi_i64(t0, n, 64);
tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi);
tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo);
tcg_gen_andi_i64(n, n, 0x3F);
tcg_gen_shl_i64(t0, lo, n);
set_avr64(a->vrt, t0, false);
tcg_gen_shl_i64(hi, hi, n);
tcg_gen_xori_i64(n, n, 63);
tcg_gen_shr_i64(lo, lo, n);
tcg_gen_shri_i64(lo, lo, 1);
tcg_gen_or_i64(hi, hi, lo);
set_avr64(a->vrt, hi, true);
tcg_temp_free_i64(hi);
tcg_temp_free_i64(lo);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(n);
return true;
}
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
TCGv_vec sat, TCGv_vec a, \