NAND Flash memory emulation and ECC calculation helpers for use by NAND controllers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2753 c046a42c-6fe2-441c-8c8c-71466251a162
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77
ecc.h
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77
ecc.h
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/*
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* Calculate Error-correcting Codes. Used by NAND Flash controllers
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* (not by NAND chips).
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GNU GPL v2.
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*/
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struct ecc_state_s {
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uint8_t cp; /* Column parity */
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uint16_t lp[2]; /* Line parity */
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uint16_t count;
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};
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/*
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* Pre-calculated 256-way 1 byte column parity. Table borrowed from Linux.
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*/
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static const uint8_t nand_ecc_precalc_table[] = {
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0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a,
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0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
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0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f,
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0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
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0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c,
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0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
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0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59,
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0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
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0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33,
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0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
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0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56,
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0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
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0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55,
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0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
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0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30,
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0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
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0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30,
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0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
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0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55,
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0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
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0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56,
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0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
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0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33,
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0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
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0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59,
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0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
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0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c,
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0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
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0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f,
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0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
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0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a,
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0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
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};
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/* Update ECC parity count. */
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static inline uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample)
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{
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uint8_t idx = nand_ecc_precalc_table[sample];
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s->cp ^= idx & 0x3f;
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if (idx & 0x40) {
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s->lp[0] ^= ~s->count;
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s->lp[1] ^= s->count;
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}
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s->count ++;
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return sample;
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}
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/* Reinitialise the counters. */
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static inline void ecc_reset(struct ecc_state_s *s)
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{
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s->lp[0] = 0x0000;
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s->lp[1] = 0x0000;
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s->cp = 0x00;
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s->count = 0;
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}
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603
hw/nand.c
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603
hw/nand.c
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/*
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* Flash NAND memory emulation. Based on "16M x 8 Bit NAND Flash
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* Memory" datasheet for the KM29U128AT / K9F2808U0A chips from
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* Samsung Electronic.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GNU GPL v2.
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*/
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#ifndef NAND_IO
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# include "vl.h"
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# define NAND_CMD_READ0 0x00
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# define NAND_CMD_READ1 0x01
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# define NAND_CMD_READ2 0x50
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# define NAND_CMD_LPREAD2 0x30
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# define NAND_CMD_NOSERIALREAD2 0x35
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# define NAND_CMD_RANDOMREAD1 0x05
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# define NAND_CMD_RANDOMREAD2 0xe0
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# define NAND_CMD_READID 0x90
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# define NAND_CMD_RESET 0xff
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# define NAND_CMD_PAGEPROGRAM1 0x80
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# define NAND_CMD_PAGEPROGRAM2 0x10
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# define NAND_CMD_CACHEPROGRAM2 0x15
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# define NAND_CMD_BLOCKERASE1 0x60
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# define NAND_CMD_BLOCKERASE2 0xd0
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# define NAND_CMD_READSTATUS 0x70
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# define NAND_CMD_COPYBACKPRG1 0x85
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# define NAND_IOSTATUS_ERROR (1 << 0)
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# define NAND_IOSTATUS_PLANE0 (1 << 1)
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# define NAND_IOSTATUS_PLANE1 (1 << 2)
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# define NAND_IOSTATUS_PLANE2 (1 << 3)
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# define NAND_IOSTATUS_PLANE3 (1 << 4)
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# define NAND_IOSTATUS_BUSY (1 << 6)
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# define NAND_IOSTATUS_UNPROTCT (1 << 7)
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# define MAX_PAGE 0x800
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# define MAX_OOB 0x40
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struct nand_flash_s {
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uint8_t manf_id, chip_id;
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int size, pages;
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int page_shift, oob_shift, erase_shift, addr_shift;
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uint8_t *storage;
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BlockDriverState *bdrv;
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int mem_oob;
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int cle, ale, ce, wp, gnd;
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uint8_t io[MAX_PAGE + MAX_OOB + 0x400];
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uint8_t *ioaddr;
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int iolen;
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uint32_t cmd, addr;
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int addrlen;
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int status;
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int offset;
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void (*blk_write)(struct nand_flash_s *s);
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void (*blk_erase)(struct nand_flash_s *s);
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void (*blk_load)(struct nand_flash_s *s, uint32_t addr, int offset);
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};
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# define NAND_NO_AUTOINCR 0x00000001
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# define NAND_BUSWIDTH_16 0x00000002
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# define NAND_NO_PADDING 0x00000004
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# define NAND_CACHEPRG 0x00000008
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# define NAND_COPYBACK 0x00000010
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# define NAND_IS_AND 0x00000020
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# define NAND_4PAGE_ARRAY 0x00000040
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# define NAND_NO_READRDY 0x00000100
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# define NAND_SAMSUNG_LP (NAND_NO_PADDING | NAND_COPYBACK)
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# define NAND_IO
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# define PAGE(addr) ((addr) >> ADDR_SHIFT)
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# define PAGE_START(page) (PAGE(page) * (PAGE_SIZE + OOB_SIZE))
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# define PAGE_MASK ((1 << ADDR_SHIFT) - 1)
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# define OOB_SHIFT (PAGE_SHIFT - 5)
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# define OOB_SIZE (1 << OOB_SHIFT)
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# define SECTOR(addr) ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT))
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# define SECTOR_OFFSET(addr) ((addr) & ((511 >> PAGE_SHIFT) << 8))
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# define PAGE_SIZE 256
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# define PAGE_SHIFT 8
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# define PAGE_SECTORS 1
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# define ADDR_SHIFT 8
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# include "nand.c"
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# define PAGE_SIZE 512
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# define PAGE_SHIFT 9
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# define PAGE_SECTORS 1
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# define ADDR_SHIFT 8
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# include "nand.c"
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# define PAGE_SIZE 2048
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# define PAGE_SHIFT 11
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# define PAGE_SECTORS 4
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# define ADDR_SHIFT 16
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# include "nand.c"
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/* Information based on Linux drivers/mtd/nand/nand_ids.c */
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struct nand_info_s {
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int size;
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int width;
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int page_shift;
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int erase_shift;
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uint32_t options;
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} nand_flash_ids[0x100] = {
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[0 ... 0xff] = { 0 },
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[0x6e] = { 1, 8, 8, 4, 0 },
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[0x64] = { 2, 8, 8, 4, 0 },
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[0x6b] = { 4, 8, 9, 4, 0 },
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[0xe8] = { 1, 8, 8, 4, 0 },
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[0xec] = { 1, 8, 8, 4, 0 },
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[0xea] = { 2, 8, 8, 4, 0 },
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[0xd5] = { 4, 8, 9, 4, 0 },
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[0xe3] = { 4, 8, 9, 4, 0 },
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[0xe5] = { 4, 8, 9, 4, 0 },
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[0xd6] = { 8, 8, 9, 4, 0 },
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[0x39] = { 8, 8, 9, 4, 0 },
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[0xe6] = { 8, 8, 9, 4, 0 },
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[0x49] = { 8, 16, 9, 4, NAND_BUSWIDTH_16 },
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[0x59] = { 8, 16, 9, 4, NAND_BUSWIDTH_16 },
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[0x33] = { 16, 8, 9, 5, 0 },
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[0x73] = { 16, 8, 9, 5, 0 },
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[0x43] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x53] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x35] = { 32, 8, 9, 5, 0 },
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[0x75] = { 32, 8, 9, 5, 0 },
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[0x45] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x55] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x36] = { 64, 8, 9, 5, 0 },
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[0x76] = { 64, 8, 9, 5, 0 },
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[0x46] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x56] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x78] = { 128, 8, 9, 5, 0 },
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[0x39] = { 128, 8, 9, 5, 0 },
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[0x79] = { 128, 8, 9, 5, 0 },
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[0x72] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x49] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x74] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x59] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x71] = { 256, 8, 9, 5, 0 },
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/*
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* These are the new chips with large page size. The pagesize and the
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* erasesize is determined from the extended id bytes
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*/
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# define LP_OPTIONS (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR)
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# define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
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/* 512 Megabit */
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[0xa2] = { 64, 8, 0, 0, LP_OPTIONS },
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[0xf2] = { 64, 8, 0, 0, LP_OPTIONS },
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[0xb2] = { 64, 16, 0, 0, LP_OPTIONS16 },
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[0xc2] = { 64, 16, 0, 0, LP_OPTIONS16 },
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/* 1 Gigabit */
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[0xa1] = { 128, 8, 0, 0, LP_OPTIONS },
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[0xf1] = { 128, 8, 0, 0, LP_OPTIONS },
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[0xb1] = { 128, 16, 0, 0, LP_OPTIONS16 },
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[0xc1] = { 128, 16, 0, 0, LP_OPTIONS16 },
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/* 2 Gigabit */
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[0xaa] = { 256, 8, 0, 0, LP_OPTIONS },
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[0xda] = { 256, 8, 0, 0, LP_OPTIONS },
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[0xba] = { 256, 16, 0, 0, LP_OPTIONS16 },
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[0xca] = { 256, 16, 0, 0, LP_OPTIONS16 },
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/* 4 Gigabit */
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[0xac] = { 512, 8, 0, 0, LP_OPTIONS },
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[0xdc] = { 512, 8, 0, 0, LP_OPTIONS },
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[0xbc] = { 512, 16, 0, 0, LP_OPTIONS16 },
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[0xcc] = { 512, 16, 0, 0, LP_OPTIONS16 },
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/* 8 Gigabit */
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[0xa3] = { 1024, 8, 0, 0, LP_OPTIONS },
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[0xd3] = { 1024, 8, 0, 0, LP_OPTIONS },
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[0xb3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
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[0xc3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
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/* 16 Gigabit */
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[0xa5] = { 2048, 8, 0, 0, LP_OPTIONS },
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[0xd5] = { 2048, 8, 0, 0, LP_OPTIONS },
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[0xb5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
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[0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
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};
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static void nand_reset(struct nand_flash_s *s)
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{
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s->cmd = NAND_CMD_READ0;
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s->addr = 0;
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s->addrlen = 0;
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s->iolen = 0;
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s->offset = 0;
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s->status &= NAND_IOSTATUS_UNPROTCT;
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}
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static void nand_command(struct nand_flash_s *s)
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{
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switch (s->cmd) {
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case NAND_CMD_READ0:
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s->iolen = 0;
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break;
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case NAND_CMD_READID:
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s->io[0] = s->manf_id;
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s->io[1] = s->chip_id;
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s->io[2] = 'Q'; /* Don't-care byte (often 0xa5) */
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if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP)
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s->io[3] = 0x15; /* Page Size, Block Size, Spare Size.. */
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else
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s->io[3] = 0xc0; /* Multi-plane */
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s->ioaddr = s->io;
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s->iolen = 4;
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break;
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case NAND_CMD_RANDOMREAD2:
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case NAND_CMD_NOSERIALREAD2:
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if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP))
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break;
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s->blk_load(s, s->addr, s->addr & ((1 << s->addr_shift) - 1));
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break;
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case NAND_CMD_RESET:
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nand_reset(s);
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break;
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case NAND_CMD_PAGEPROGRAM1:
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s->ioaddr = s->io;
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s->iolen = 0;
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break;
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case NAND_CMD_PAGEPROGRAM2:
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if (s->wp) {
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s->blk_write(s);
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}
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break;
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case NAND_CMD_BLOCKERASE1:
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break;
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case NAND_CMD_BLOCKERASE2:
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if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP)
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s->addr <<= 16;
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else
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s->addr <<= 8;
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if (s->wp) {
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s->blk_erase(s);
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}
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break;
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case NAND_CMD_READSTATUS:
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s->io[0] = s->status;
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s->ioaddr = s->io;
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s->iolen = 1;
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break;
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default:
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printf("%s: Unknown NAND command 0x%02x\n", __FUNCTION__, s->cmd);
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}
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}
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/*
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* Chip inputs are CLE, ALE, CE, WP, GND and eight I/O pins. Chip
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* outputs are R/B and eight I/O pins.
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*
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* CE, WP and R/B are active low.
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*/
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void nand_setpins(struct nand_flash_s *s,
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int cle, int ale, int ce, int wp, int gnd)
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{
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s->cle = cle;
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s->ale = ale;
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s->ce = ce;
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s->wp = wp;
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s->gnd = gnd;
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if (wp)
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s->status |= NAND_IOSTATUS_UNPROTCT;
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else
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s->status &= ~NAND_IOSTATUS_UNPROTCT;
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}
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void nand_getpins(struct nand_flash_s *s, int *rb)
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{
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*rb = 1;
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}
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void nand_setio(struct nand_flash_s *s, uint8_t value)
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{
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if (!s->ce && s->cle) {
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if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
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if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2)
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return;
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if (value == NAND_CMD_RANDOMREAD1) {
|
||||
s->addr &= ~((1 << s->addr_shift) - 1);
|
||||
s->addrlen = 0;
|
||||
return;
|
||||
}
|
||||
}
|
||||
if (value == NAND_CMD_READ0)
|
||||
s->offset = 0;
|
||||
else if (value == NAND_CMD_READ1) {
|
||||
s->offset = 0x100;
|
||||
value = NAND_CMD_READ0;
|
||||
}
|
||||
else if (value == NAND_CMD_READ2) {
|
||||
s->offset = 1 << s->page_shift;
|
||||
value = NAND_CMD_READ0;
|
||||
}
|
||||
|
||||
s->cmd = value;
|
||||
|
||||
if (s->cmd == NAND_CMD_READSTATUS ||
|
||||
s->cmd == NAND_CMD_PAGEPROGRAM2 ||
|
||||
s->cmd == NAND_CMD_BLOCKERASE1 ||
|
||||
s->cmd == NAND_CMD_BLOCKERASE2 ||
|
||||
s->cmd == NAND_CMD_NOSERIALREAD2 ||
|
||||
s->cmd == NAND_CMD_RANDOMREAD2 ||
|
||||
s->cmd == NAND_CMD_RESET)
|
||||
nand_command(s);
|
||||
|
||||
if (s->cmd != NAND_CMD_RANDOMREAD2) {
|
||||
s->addrlen = 0;
|
||||
s->addr = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (s->ale) {
|
||||
s->addr |= value << (s->addrlen * 8);
|
||||
s->addrlen ++;
|
||||
|
||||
if (s->addrlen == 1 && s->cmd == NAND_CMD_READID)
|
||||
nand_command(s);
|
||||
|
||||
if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
|
||||
s->addrlen == 3 && (
|
||||
s->cmd == NAND_CMD_READ0 ||
|
||||
s->cmd == NAND_CMD_PAGEPROGRAM1))
|
||||
nand_command(s);
|
||||
if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
|
||||
s->addrlen == 4 && (
|
||||
s->cmd == NAND_CMD_READ0 ||
|
||||
s->cmd == NAND_CMD_PAGEPROGRAM1))
|
||||
nand_command(s);
|
||||
}
|
||||
|
||||
if (!s->cle && !s->ale && s->cmd == NAND_CMD_PAGEPROGRAM1) {
|
||||
if (s->iolen < (1 << s->page_shift) + (1 << s->oob_shift))
|
||||
s->io[s->iolen ++] = value;
|
||||
} else if (!s->cle && !s->ale && s->cmd == NAND_CMD_COPYBACKPRG1) {
|
||||
if ((s->addr & ((1 << s->addr_shift) - 1)) <
|
||||
(1 << s->page_shift) + (1 << s->oob_shift)) {
|
||||
s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] = value;
|
||||
s->addr ++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t nand_getio(struct nand_flash_s *s)
|
||||
{
|
||||
int offset;
|
||||
|
||||
/* Allow sequential reading */
|
||||
if (!s->iolen && s->cmd == NAND_CMD_READ0) {
|
||||
offset = (s->addr & ((1 << s->addr_shift) - 1)) + s->offset;
|
||||
s->offset = 0;
|
||||
|
||||
s->blk_load(s, s->addr, offset);
|
||||
if (s->gnd)
|
||||
s->iolen = (1 << s->page_shift) - offset;
|
||||
else
|
||||
s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
|
||||
}
|
||||
|
||||
if (s->ce || s->iolen <= 0)
|
||||
return 0;
|
||||
|
||||
s->iolen --;
|
||||
return *(s->ioaddr ++);
|
||||
}
|
||||
|
||||
struct nand_flash_s *nand_init(int manf_id, int chip_id)
|
||||
{
|
||||
int pagesize;
|
||||
struct nand_flash_s *s;
|
||||
|
||||
if (nand_flash_ids[chip_id].size == 0) {
|
||||
cpu_abort(cpu_single_env, "%s: Unsupported NAND chip ID.\n",
|
||||
__FUNCTION__);
|
||||
}
|
||||
|
||||
s = (struct nand_flash_s *) qemu_mallocz(sizeof(struct nand_flash_s));
|
||||
s->bdrv = mtd_bdrv;
|
||||
s->manf_id = manf_id;
|
||||
s->chip_id = chip_id;
|
||||
s->size = nand_flash_ids[s->chip_id].size << 20;
|
||||
if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
|
||||
s->page_shift = 11;
|
||||
s->erase_shift = 6;
|
||||
} else {
|
||||
s->page_shift = nand_flash_ids[s->chip_id].page_shift;
|
||||
s->erase_shift = nand_flash_ids[s->chip_id].erase_shift;
|
||||
}
|
||||
|
||||
switch (1 << s->page_shift) {
|
||||
case 256:
|
||||
nand_init_256(s);
|
||||
break;
|
||||
case 512:
|
||||
nand_init_512(s);
|
||||
break;
|
||||
case 2048:
|
||||
nand_init_2048(s);
|
||||
break;
|
||||
default:
|
||||
cpu_abort(cpu_single_env, "%s: Unsupported NAND block size.\n",
|
||||
__FUNCTION__);
|
||||
}
|
||||
|
||||
pagesize = 1 << s->oob_shift;
|
||||
s->mem_oob = 1;
|
||||
if (s->bdrv && bdrv_getlength(s->bdrv) >=
|
||||
(s->pages << s->page_shift) + (s->pages << s->oob_shift)) {
|
||||
pagesize = 0;
|
||||
s->mem_oob = 0;
|
||||
}
|
||||
|
||||
if (!s->bdrv)
|
||||
pagesize += 1 << s->page_shift;
|
||||
if (pagesize)
|
||||
s->storage = (uint8_t *) memset(qemu_malloc(s->pages * pagesize),
|
||||
0xff, s->pages * pagesize);
|
||||
return s;
|
||||
}
|
||||
|
||||
void nand_done(struct nand_flash_s *s)
|
||||
{
|
||||
if (s->bdrv) {
|
||||
bdrv_close(s->bdrv);
|
||||
bdrv_delete(s->bdrv);
|
||||
}
|
||||
|
||||
if (!s->bdrv || s->mem_oob)
|
||||
free(s->storage);
|
||||
|
||||
free(s);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
/* Program a single page */
|
||||
static void glue(nand_blk_write_, PAGE_SIZE)(struct nand_flash_s *s)
|
||||
{
|
||||
uint32_t off, page, sector, soff;
|
||||
uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200];
|
||||
if (PAGE(s->addr) >= s->pages)
|
||||
return;
|
||||
|
||||
if (!s->bdrv) {
|
||||
memcpy(s->storage + PAGE_START(s->addr) + (s->addr & PAGE_MASK) +
|
||||
s->offset, s->io, s->iolen);
|
||||
} else if (s->mem_oob) {
|
||||
sector = SECTOR(s->addr);
|
||||
off = (s->addr & PAGE_MASK) + s->offset;
|
||||
soff = SECTOR_OFFSET(s->addr);
|
||||
if (bdrv_read(s->bdrv, sector, iobuf, PAGE_SECTORS) == -1) {
|
||||
printf("%s: read error in sector %i\n", __FUNCTION__, sector);
|
||||
return;
|
||||
}
|
||||
|
||||
memcpy(iobuf + (soff | off), s->io, MIN(s->iolen, PAGE_SIZE - off));
|
||||
if (off + s->iolen > PAGE_SIZE) {
|
||||
page = PAGE(s->addr);
|
||||
memcpy(s->storage + (page << OOB_SHIFT), s->io + PAGE_SIZE - off,
|
||||
MIN(OOB_SIZE, off + s->iolen - PAGE_SIZE));
|
||||
}
|
||||
|
||||
if (bdrv_write(s->bdrv, sector, iobuf, PAGE_SECTORS) == -1)
|
||||
printf("%s: write error in sector %i\n", __FUNCTION__, sector);
|
||||
} else {
|
||||
off = PAGE_START(s->addr) + (s->addr & PAGE_MASK) + s->offset;
|
||||
sector = off >> 9;
|
||||
soff = off & 0x1ff;
|
||||
if (bdrv_read(s->bdrv, sector, iobuf, PAGE_SECTORS + 2) == -1) {
|
||||
printf("%s: read error in sector %i\n", __FUNCTION__, sector);
|
||||
return;
|
||||
}
|
||||
|
||||
memcpy(iobuf + soff, s->io, s->iolen);
|
||||
|
||||
if (bdrv_write(s->bdrv, sector, iobuf, PAGE_SECTORS + 2) == -1)
|
||||
printf("%s: write error in sector %i\n", __FUNCTION__, sector);
|
||||
}
|
||||
s->offset = 0;
|
||||
}
|
||||
|
||||
/* Erase a single block */
|
||||
static void glue(nand_blk_erase_, PAGE_SIZE)(struct nand_flash_s *s)
|
||||
{
|
||||
uint32_t i, page, addr;
|
||||
uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, };
|
||||
addr = s->addr & ~((1 << (ADDR_SHIFT + s->erase_shift)) - 1);
|
||||
|
||||
if (PAGE(addr) >= s->pages)
|
||||
return;
|
||||
|
||||
if (!s->bdrv) {
|
||||
memset(s->storage + PAGE_START(addr),
|
||||
0xff, (PAGE_SIZE + OOB_SIZE) << s->erase_shift);
|
||||
} else if (s->mem_oob) {
|
||||
memset(s->storage + (PAGE(addr) << OOB_SHIFT),
|
||||
0xff, OOB_SIZE << s->erase_shift);
|
||||
i = SECTOR(addr);
|
||||
page = SECTOR(addr + (ADDR_SHIFT + s->erase_shift));
|
||||
for (; i < page; i ++)
|
||||
if (bdrv_write(s->bdrv, i, iobuf, 1) == -1)
|
||||
printf("%s: write error in sector %i\n", __FUNCTION__, i);
|
||||
} else {
|
||||
addr = PAGE_START(addr);
|
||||
page = addr >> 9;
|
||||
if (bdrv_read(s->bdrv, page, iobuf, 1) == -1)
|
||||
printf("%s: read error in sector %i\n", __FUNCTION__, page);
|
||||
memset(iobuf + (addr & 0x1ff), 0xff, (~addr & 0x1ff) + 1);
|
||||
if (bdrv_write(s->bdrv, page, iobuf, 1) == -1)
|
||||
printf("%s: write error in sector %i\n", __FUNCTION__, page);
|
||||
|
||||
memset(iobuf, 0xff, 0x200);
|
||||
i = (addr & ~0x1ff) + 0x200;
|
||||
for (addr += ((PAGE_SIZE + OOB_SIZE) << s->erase_shift) - 0x200;
|
||||
i < addr; i += 0x200)
|
||||
if (bdrv_write(s->bdrv, i >> 9, iobuf, 1) == -1)
|
||||
printf("%s: write error in sector %i\n", __FUNCTION__, i >> 9);
|
||||
|
||||
page = i >> 9;
|
||||
if (bdrv_read(s->bdrv, page, iobuf, 1) == -1)
|
||||
printf("%s: read error in sector %i\n", __FUNCTION__, page);
|
||||
memset(iobuf, 0xff, addr & 0x1ff);
|
||||
if (bdrv_write(s->bdrv, page, iobuf, 1) == -1)
|
||||
printf("%s: write error in sector %i\n", __FUNCTION__, page);
|
||||
}
|
||||
}
|
||||
|
||||
static void glue(nand_blk_load_, PAGE_SIZE)(struct nand_flash_s *s,
|
||||
uint32_t addr, int offset)
|
||||
{
|
||||
if (PAGE(addr) >= s->pages)
|
||||
return;
|
||||
|
||||
if (s->bdrv) {
|
||||
if (s->mem_oob) {
|
||||
if (bdrv_read(s->bdrv, SECTOR(addr), s->io, PAGE_SECTORS) == -1)
|
||||
printf("%s: read error in sector %i\n",
|
||||
__FUNCTION__, SECTOR(addr));
|
||||
memcpy(s->io + SECTOR_OFFSET(s->addr) + PAGE_SIZE,
|
||||
s->storage + (PAGE(s->addr) << OOB_SHIFT),
|
||||
OOB_SIZE);
|
||||
s->ioaddr = s->io + SECTOR_OFFSET(s->addr) + offset;
|
||||
} else {
|
||||
if (bdrv_read(s->bdrv, PAGE_START(addr) >> 9,
|
||||
s->io, (PAGE_SECTORS + 2)) == -1)
|
||||
printf("%s: read error in sector %i\n",
|
||||
__FUNCTION__, PAGE_START(addr) >> 9);
|
||||
s->ioaddr = s->io + (PAGE_START(addr) & 0x1ff) + offset;
|
||||
}
|
||||
} else {
|
||||
memcpy(s->io, s->storage + PAGE_START(s->addr) +
|
||||
offset, PAGE_SIZE + OOB_SIZE - offset);
|
||||
s->ioaddr = s->io;
|
||||
}
|
||||
|
||||
s->addr &= PAGE_SIZE - 1;
|
||||
s->addr += PAGE_SIZE;
|
||||
}
|
||||
|
||||
static void glue(nand_init_, PAGE_SIZE)(struct nand_flash_s *s)
|
||||
{
|
||||
s->oob_shift = PAGE_SHIFT - 5;
|
||||
s->pages = s->size >> PAGE_SHIFT;
|
||||
s->addr_shift = ADDR_SHIFT;
|
||||
|
||||
s->blk_erase = glue(nand_blk_erase_, PAGE_SIZE);
|
||||
s->blk_write = glue(nand_blk_write_, PAGE_SIZE);
|
||||
s->blk_load = glue(nand_blk_load_, PAGE_SIZE);
|
||||
}
|
||||
|
||||
# undef PAGE_SIZE
|
||||
# undef PAGE_SHIFT
|
||||
# undef PAGE_SECTORS
|
||||
# undef ADDR_SHIFT
|
||||
#endif /* NAND_IO */
|
||||
21
vl.c
21
vl.c
@ -140,6 +140,7 @@ IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
|
||||
BlockDriverState *bs_table[MAX_DISKS + 1], *fd_table[MAX_FD];
|
||||
BlockDriverState *pflash_table[MAX_PFLASH];
|
||||
BlockDriverState *sd_bdrv;
|
||||
BlockDriverState *mtd_bdrv;
|
||||
/* point to the block driver where the snapshots are managed */
|
||||
BlockDriverState *bs_snapshots;
|
||||
int vga_ram_size;
|
||||
@ -6419,6 +6420,7 @@ void help(void)
|
||||
"-hda/-hdb file use 'file' as IDE hard disk 0/1 image\n"
|
||||
"-hdc/-hdd file use 'file' as IDE hard disk 2/3 image\n"
|
||||
"-cdrom file use 'file' as IDE cdrom image (cdrom is ide1 master)\n"
|
||||
"-mtdblock file use 'file' as on-board Flash memory image\n"
|
||||
"-sd file use 'file' as SecureDigital card image\n"
|
||||
"-pflash file use 'file' as a parallel flash image\n"
|
||||
"-boot [a|c|d|n] boot on floppy (a), hard disk (c), CD-ROM (d), or network (n)\n"
|
||||
@ -6559,6 +6561,7 @@ enum {
|
||||
QEMU_OPTION_hdc,
|
||||
QEMU_OPTION_hdd,
|
||||
QEMU_OPTION_cdrom,
|
||||
QEMU_OPTION_mtdblock,
|
||||
QEMU_OPTION_sd,
|
||||
QEMU_OPTION_pflash,
|
||||
QEMU_OPTION_boot,
|
||||
@ -6640,6 +6643,7 @@ const QEMUOption qemu_options[] = {
|
||||
{ "hdc", HAS_ARG, QEMU_OPTION_hdc },
|
||||
{ "hdd", HAS_ARG, QEMU_OPTION_hdd },
|
||||
{ "cdrom", HAS_ARG, QEMU_OPTION_cdrom },
|
||||
{ "mtdblock", HAS_ARG, QEMU_OPTION_mtdblock },
|
||||
{ "sd", HAS_ARG, QEMU_OPTION_sd },
|
||||
{ "pflash", HAS_ARG, QEMU_OPTION_pflash },
|
||||
{ "boot", HAS_ARG, QEMU_OPTION_boot },
|
||||
@ -6944,6 +6948,7 @@ int main(int argc, char **argv)
|
||||
const char *hd_filename[MAX_DISKS], *fd_filename[MAX_FD];
|
||||
const char *pflash_filename[MAX_PFLASH];
|
||||
const char *sd_filename;
|
||||
const char *mtd_filename;
|
||||
const char *kernel_filename, *kernel_cmdline;
|
||||
DisplayState *ds = &display_state;
|
||||
int cyls, heads, secs, translation;
|
||||
@ -7008,6 +7013,7 @@ int main(int argc, char **argv)
|
||||
pflash_filename[i] = NULL;
|
||||
pflash_index = 0;
|
||||
sd_filename = NULL;
|
||||
mtd_filename = NULL;
|
||||
ram_size = DEFAULT_RAM_SIZE * 1024 * 1024;
|
||||
vga_ram_size = VGA_RAM_SIZE;
|
||||
#ifdef CONFIG_GDBSTUB
|
||||
@ -7126,6 +7132,9 @@ int main(int argc, char **argv)
|
||||
cdrom_index = -1;
|
||||
}
|
||||
break;
|
||||
case QEMU_OPTION_mtdblock:
|
||||
mtd_filename = optarg;
|
||||
break;
|
||||
case QEMU_OPTION_sd:
|
||||
sd_filename = optarg;
|
||||
break;
|
||||
@ -7678,6 +7687,18 @@ int main(int argc, char **argv)
|
||||
qemu_key_check(sd_bdrv, sd_filename);
|
||||
}
|
||||
|
||||
if (mtd_filename) {
|
||||
mtd_bdrv = bdrv_new ("mtd");
|
||||
if (bdrv_open(mtd_bdrv, mtd_filename,
|
||||
snapshot ? BDRV_O_SNAPSHOT : 0) < 0 ||
|
||||
qemu_key_check(mtd_bdrv, mtd_filename)) {
|
||||
fprintf(stderr, "qemu: could not open Flash image %s\n",
|
||||
mtd_filename);
|
||||
bdrv_delete(mtd_bdrv);
|
||||
mtd_bdrv = 0;
|
||||
}
|
||||
}
|
||||
|
||||
register_savevm("timer", 0, 2, timer_save, timer_load, NULL);
|
||||
register_savevm("ram", 0, 2, ram_save, ram_load, NULL);
|
||||
|
||||
|
||||
22
vl.h
22
vl.h
@ -967,6 +967,7 @@ extern uint8_t _translate_keycode(const int key);
|
||||
|
||||
extern BlockDriverState *bs_table[MAX_DISKS + 1];
|
||||
extern BlockDriverState *sd_bdrv;
|
||||
extern BlockDriverState *mtd_bdrv;
|
||||
|
||||
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
|
||||
BlockDriverState *hd0, BlockDriverState *hd1);
|
||||
@ -1478,6 +1479,27 @@ pflash_t *pflash_register (target_ulong base, ram_addr_t off,
|
||||
uint16_t id0, uint16_t id1,
|
||||
uint16_t id2, uint16_t id3);
|
||||
|
||||
/* nand.c */
|
||||
struct nand_flash_s;
|
||||
struct nand_flash_s *nand_init(int manf_id, int chip_id);
|
||||
void nand_done(struct nand_flash_s *s);
|
||||
void nand_setpins(struct nand_flash_s *s,
|
||||
int cle, int ale, int ce, int wp, int gnd);
|
||||
void nand_getpins(struct nand_flash_s *s, int *rb);
|
||||
void nand_setio(struct nand_flash_s *s, uint8_t value);
|
||||
uint8_t nand_getio(struct nand_flash_s *s);
|
||||
|
||||
#define NAND_MFR_TOSHIBA 0x98
|
||||
#define NAND_MFR_SAMSUNG 0xec
|
||||
#define NAND_MFR_FUJITSU 0x04
|
||||
#define NAND_MFR_NATIONAL 0x8f
|
||||
#define NAND_MFR_RENESAS 0x07
|
||||
#define NAND_MFR_STMICRO 0x20
|
||||
#define NAND_MFR_HYNIX 0xad
|
||||
#define NAND_MFR_MICRON 0x2c
|
||||
|
||||
#include "ecc.h"
|
||||
|
||||
/* PCMCIA/Cardbus */
|
||||
|
||||
struct pcmcia_socket_s {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user