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target/riscv: remove cpu->cfg.ext_v 

Create a new "v" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are
replaced with riscv_has_ext(env, RVV).

Remove the old "v" property and 'ext_v' from RISCVCPUConfig.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-04-06 15:03:47 -03:00 committed by Alistair Francis
parent 64f4b541c5
commit 3e7674fd1a
2 changed files with 5 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
target/riscv/cpu.c
View File

@ -883,7 +883,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
}
/* The V vector extension depends on the Zve64d extension */
if (cpu->cfg.ext_v) {
if (riscv_has_ext(env, RVV)) {
cpu->cfg.ext_zve64d = true;
}
@ -1018,7 +1018,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_zksh = true;
}
if (cpu->cfg.ext_v) {
if (riscv_has_ext(env, RVV)) {
int vext_version = VEXT_VERSION_1_00_0;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
@ -1175,7 +1175,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVH)) {
ext |= RVH;
}
if (riscv_cpu_cfg(env)->ext_v) {
if (riscv_has_ext(env, RVV)) {
ext |= RVV;
}
if (riscv_has_ext(env, RVJ)) {
@ -1513,6 +1513,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVH, .enabled = true},
{.name = "x-j", .description = "Dynamic translated languages",
.misa_bit = RVJ, .enabled = false},
{.name = "v", .description = "Vector operations",
.misa_bit = RVV, .enabled = false},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@ -1536,7 +1538,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
@ -1638,7 +1639,6 @@ static Property riscv_cpu_extensions[] = {
static void register_cpu_props(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
uint32_t misa_ext = cpu->env.misa_ext;
Property *prop;
DeviceState *dev = DEVICE(obj);
@ -1648,8 +1648,6 @@ static void register_cpu_props(Object *obj)
* later on.
*/
if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_v = misa_ext & RVV;
/*
* We don't want to set the default riscv_cpu_extensions
* in this case.

1
target/riscv/cpu.h
View File

@ -423,7 +423,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
bool ext_v;
bool ext_zba;
bool ext_zbb;
bool ext_zbc;