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target/ppc: isolated cpu init from translation logic

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finished isolation of CPU initialization logic from
translation logic. CPU initialization now only has common code
and may or may not call accelerator-specific code, as the
build options require.

Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20210507115551.11436-1-bruno.larsen@eldorado.org.br>
[dwg: Fix compile error with clang linux-user builds]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Bruno Larsen (billionai) 2021-05-07 08:55:51 -03:00 committed by David Gibson
parent a829cec3a3
commit 3e770bf7a9
4 changed files with 13 additions and 2 deletions
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8
target/ppc/translate_init.c.inc → target/ppc/cpu_init.c
View File

@ -18,6 +18,7 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "disas/dis-asm.h"
#include "exec/gdbstub.h"
#include "kvm_ppc.h"
@ -42,6 +43,11 @@
#include "fpu/softfloat.h"
#include "qapi/qapi-commands-machine-target.h"
#include "exec/helper-proto.h"
#include "helper_regs.h"
#include "internal.h"
#include "spr_tcg.h"
/* #define PPC_DEBUG_SPR */
/* #define USE_APPLE_GDB */
@ -1171,6 +1177,7 @@ static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
0x00000000);
}
#if !defined(CONFIG_USER_ONLY)
static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
uint32_t maxsize, uint32_t flags,
uint32_t nentries)
@ -1180,6 +1187,7 @@ static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
(maxsize << TLBnCFG_MAXSIZE_SHIFT) |
flags | nentries;
}
#endif /* !CONFIG_USER_ONLY */
/* BookE 2.06 storage control registers */
static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,

1
target/ppc/meson.build
View File

@ -2,6 +2,7 @@ ppc_ss = ss.source_set()
ppc_ss.add(files(
'cpu-models.c',
'cpu.c',
'cpu_init.c',
'dfp_helper.c',
'excp_helper.c',
'fpu_helper.c',

2
target/ppc/spr_tcg.h
View File

@ -19,6 +19,8 @@
#ifndef SPR_TCG_H
#define SPR_TCG_H
#define SPR_NOACCESS (&spr_noaccess)
/* prototypes for readers and writers for SPRs */
void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
void spr_read_generic(DisasContext *ctx, int gprn, int sprn);

4
target/ppc/translate.c
View File

@ -38,6 +38,8 @@
#include "qemu/atomic128.h"
#include "spr_tcg.h"
#include "qemu/qemu-print.h"
#include "qapi/error.h"
#define CPU_SINGLE_STEP 0x1
#define CPU_BRANCH_STEP 0x2
@ -380,7 +382,6 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
printf("ERROR: try to access SPR %d !\n", sprn);
#endif
}
#define SPR_NOACCESS (&spr_noaccess)
/* #define PPC_DUMP_SPR_ACCESSES */
@ -8617,7 +8618,6 @@ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
};
#include "helper_regs.h"
#include "translate_init.c.inc"
/*****************************************************************************/
/* Misc PowerPC helpers */