target/ppc: isolated cpu init from translation logic
finished isolation of CPU initialization logic from translation logic. CPU initialization now only has common code and may or may not call accelerator-specific code, as the build options require. Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20210507115551.11436-1-bruno.larsen@eldorado.org.br> [dwg: Fix compile error with clang linux-user builds] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -18,6 +18,7 @@
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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#include "qemu/osdep.h"
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#include "disas/dis-asm.h"
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#include "disas/dis-asm.h"
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#include "exec/gdbstub.h"
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#include "exec/gdbstub.h"
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#include "kvm_ppc.h"
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#include "kvm_ppc.h"
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@ -42,6 +43,11 @@
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#include "fpu/softfloat.h"
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#include "fpu/softfloat.h"
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#include "qapi/qapi-commands-machine-target.h"
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#include "qapi/qapi-commands-machine-target.h"
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#include "exec/helper-proto.h"
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#include "helper_regs.h"
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#include "internal.h"
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#include "spr_tcg.h"
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/* #define PPC_DEBUG_SPR */
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/* #define PPC_DEBUG_SPR */
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/* #define USE_APPLE_GDB */
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/* #define USE_APPLE_GDB */
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@ -1171,6 +1177,7 @@ static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
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0x00000000);
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0x00000000);
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}
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}
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#if !defined(CONFIG_USER_ONLY)
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static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
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static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
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uint32_t maxsize, uint32_t flags,
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uint32_t maxsize, uint32_t flags,
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uint32_t nentries)
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uint32_t nentries)
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@ -1180,6 +1187,7 @@ static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
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(maxsize << TLBnCFG_MAXSIZE_SHIFT) |
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(maxsize << TLBnCFG_MAXSIZE_SHIFT) |
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flags | nentries;
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flags | nentries;
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}
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}
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#endif /* !CONFIG_USER_ONLY */
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/* BookE 2.06 storage control registers */
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/* BookE 2.06 storage control registers */
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static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
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static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
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@ -2,6 +2,7 @@ ppc_ss = ss.source_set()
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ppc_ss.add(files(
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ppc_ss.add(files(
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'cpu-models.c',
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'cpu-models.c',
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'cpu.c',
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'cpu.c',
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'cpu_init.c',
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'dfp_helper.c',
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'dfp_helper.c',
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'excp_helper.c',
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'excp_helper.c',
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'fpu_helper.c',
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'fpu_helper.c',
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@ -19,6 +19,8 @@
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#ifndef SPR_TCG_H
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#ifndef SPR_TCG_H
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#define SPR_TCG_H
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#define SPR_TCG_H
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#define SPR_NOACCESS (&spr_noaccess)
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/* prototypes for readers and writers for SPRs */
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/* prototypes for readers and writers for SPRs */
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void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
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void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
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void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
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void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
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@ -38,6 +38,8 @@
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#include "qemu/atomic128.h"
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#include "qemu/atomic128.h"
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#include "spr_tcg.h"
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#include "spr_tcg.h"
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#include "qemu/qemu-print.h"
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#include "qapi/error.h"
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#define CPU_SINGLE_STEP 0x1
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#define CPU_SINGLE_STEP 0x1
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#define CPU_BRANCH_STEP 0x2
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#define CPU_BRANCH_STEP 0x2
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@ -380,7 +382,6 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
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printf("ERROR: try to access SPR %d !\n", sprn);
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printf("ERROR: try to access SPR %d !\n", sprn);
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#endif
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#endif
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}
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}
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#define SPR_NOACCESS (&spr_noaccess)
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/* #define PPC_DUMP_SPR_ACCESSES */
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/* #define PPC_DUMP_SPR_ACCESSES */
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@ -8617,7 +8618,6 @@ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
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};
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};
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#include "helper_regs.h"
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#include "helper_regs.h"
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#include "translate_init.c.inc"
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/*****************************************************************************/
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/*****************************************************************************/
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/* Misc PowerPC helpers */
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/* Misc PowerPC helpers */
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