OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

docs/system/riscv: Correct the indentation level of supported devices 

The supported device bullet list has an additional space before each
entry, which makes a wrong indentation level. Correct it.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-5-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2021-04-30 15:12:59 +08:00 committed by Alistair Francis
parent 60bb5407f0
commit 3ede8967c8
2 changed files with 25 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
docs/system/riscv/microchip-icicle-kit.rst
View File

@ -15,16 +15,16 @@ Supported devices
The ``microchip-icicle-kit`` machine supports the following devices:
* 1 E51 core
* 4 U54 cores
* Core Level Interruptor (CLINT)
* Platform-Level Interrupt Controller (PLIC)
* L2 Loosely Integrated Memory (L2-LIM)
* DDR memory controller
* 5 MMUARTs
* 1 DMA controller
* 2 GEM Ethernet controllers
* 1 SDHC storage controller
* 1 E51 core
* 4 U54 cores
* Core Level Interruptor (CLINT)
* Platform-Level Interrupt Controller (PLIC)
* L2 Loosely Integrated Memory (L2-LIM)
* DDR memory controller
* 5 MMUARTs
* 1 DMA controller
* 2 GEM Ethernet controllers
* 1 SDHC storage controller
Boot options
------------

30
docs/system/riscv/sifive_u.rst
View File

@ -9,21 +9,21 @@ Supported devices
The ``sifive_u`` machine supports the following devices:
* 1 E51 / E31 core
* Up to 4 U54 / U34 cores
* Core Level Interruptor (CLINT)
* Platform-Level Interrupt Controller (PLIC)
* Power, Reset, Clock, Interrupt (PRCI)
* L2 Loosely Integrated Memory (L2-LIM)
* DDR memory controller
* 2 UARTs
* 1 GEM Ethernet controller
* 1 GPIO controller
* 1 One-Time Programmable (OTP) memory with stored serial number
* 1 DMA controller
* 2 QSPI controllers
* 1 ISSI 25WP256 flash
* 1 SD card in SPI mode
* 1 E51 / E31 core
* Up to 4 U54 / U34 cores
* Core Level Interruptor (CLINT)
* Platform-Level Interrupt Controller (PLIC)
* Power, Reset, Clock, Interrupt (PRCI)
* L2 Loosely Integrated Memory (L2-LIM)
* DDR memory controller
* 2 UARTs
* 1 GEM Ethernet controller
* 1 GPIO controller
* 1 One-Time Programmable (OTP) memory with stored serial number
* 1 DMA controller
* 2 QSPI controllers
* 1 ISSI 25WP256 flash
* 1 SD card in SPI mode
Please note the real world HiFive Unleashed board has a fixed configuration of
1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode.