target/riscv: Simplify check for Zve32f and Zve64f
V/Zve64f depend on Zve32f, so we can only check Zve32f in these cases. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-9-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -51,7 +51,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
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*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
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*cs_base = 0;
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if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
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if (cpu->cfg.ext_zve32f) {
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/*
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* If env->vl equals to VLMAX, we can use generic vector operation
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* expanders (GVEC) to accerlate the vector operations.
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@ -93,8 +93,7 @@ static RISCVException vs(CPURISCVState *env, int csrno)
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CPUState *cs = env_cpu(env);
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RISCVCPU *cpu = RISCV_CPU(cs);
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if (env->misa_ext & RVV ||
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cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
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if (cpu->cfg.ext_zve32f) {
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
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return RISCV_EXCP_ILLEGAL_INST;
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@ -173,9 +173,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
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{
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TCGv s1, dst;
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if (!require_rvv(s) ||
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!(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
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s->cfg_ptr->ext_zve64f)) {
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if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
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return false;
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}
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@ -210,9 +208,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
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{
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TCGv dst;
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if (!require_rvv(s) ||
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!(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
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s->cfg_ptr->ext_zve64f)) {
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if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
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return false;
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}
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