hardware interrupt support - support forfull ring 0 exception simulation
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@260 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
f76af4b3f3
commit
3fb2ded1d5
340
cpu-exec.c
340
cpu-exec.c
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@ -29,6 +29,8 @@
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//#define DEBUG_EXEC
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//#define DEBUG_SIGNAL
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/* enable it to have a fully working x86 emulator for ring 0 */
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//#define RING0_HACKS
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#if defined(TARGET_ARM)
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/* XXX: unify with i386 target */
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@ -140,146 +142,195 @@ int cpu_exec(CPUState *env1)
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#error unsupported target CPU
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#endif
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env->interrupt_request = 0;
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env->exception_index = -1;
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/* prepare setjmp context for exception handling */
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if (setjmp(env->jmp_env) == 0) {
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T0 = 0; /* force lookup of first TB */
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for(;;) {
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#ifdef __sparc__
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/* g1 can be modified by some libc? functions */
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tmp_T0 = T0;
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#endif
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if (env->interrupt_request) {
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env->exception_index = EXCP_INTERRUPT;
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cpu_loop_exit();
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for(;;) {
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if (setjmp(env->jmp_env) == 0) {
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/* if an exception is pending, we execute it here */
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if (env->exception_index >= 0) {
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if (env->exception_index >= EXCP_INTERRUPT) {
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/* exit request from the cpu execution loop */
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ret = env->exception_index;
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break;
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} else if (env->user_mode_only) {
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/* if user mode only, we simulate a fake exception
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which will be hanlded outside the cpu execution
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loop */
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do_interrupt_user(env->exception_index,
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env->exception_is_int,
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env->error_code,
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env->exception_next_eip);
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ret = env->exception_index;
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break;
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} else {
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/* simulate a real cpu exception. On i386, it can
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trigger new exceptions, but we do not handle
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double or triple faults yet. */
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do_interrupt(env->exception_index,
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env->exception_is_int,
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env->error_code,
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env->exception_next_eip);
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}
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env->exception_index = -1;
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}
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#ifdef DEBUG_EXEC
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if (loglevel) {
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#if defined(TARGET_I386)
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/* restore flags in standard format */
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env->regs[R_EAX] = EAX;
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env->regs[R_EBX] = EBX;
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env->regs[R_ECX] = ECX;
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env->regs[R_EDX] = EDX;
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env->regs[R_ESI] = ESI;
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env->regs[R_EDI] = EDI;
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env->regs[R_EBP] = EBP;
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env->regs[R_ESP] = ESP;
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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cpu_x86_dump_state(env, logfile, 0);
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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/* if hardware interrupt pending, we execute it */
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if (env->hard_interrupt_request &&
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(env->eflags & IF_MASK)) {
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int intno;
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intno = cpu_x86_get_pic_interrupt(env);
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if (loglevel) {
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fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
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}
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do_interrupt(intno, 0, 0, 0);
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env->hard_interrupt_request = 0;
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}
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#endif
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T0 = 0; /* force lookup of first TB */
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for(;;) {
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#ifdef __sparc__
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/* g1 can be modified by some libc? functions */
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tmp_T0 = T0;
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#endif
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if (env->interrupt_request) {
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env->exception_index = EXCP_INTERRUPT;
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cpu_loop_exit();
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}
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#ifdef DEBUG_EXEC
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if (loglevel) {
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#if defined(TARGET_I386)
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/* restore flags in standard format */
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env->regs[R_EAX] = EAX;
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env->regs[R_EBX] = EBX;
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env->regs[R_ECX] = ECX;
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env->regs[R_EDX] = EDX;
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env->regs[R_ESI] = ESI;
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env->regs[R_EDI] = EDI;
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env->regs[R_EBP] = EBP;
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env->regs[R_ESP] = ESP;
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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cpu_x86_dump_state(env, logfile, 0);
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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#elif defined(TARGET_ARM)
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cpu_arm_dump_state(env, logfile, 0);
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cpu_arm_dump_state(env, logfile, 0);
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#else
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#error unsupported target CPU
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#endif
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}
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}
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#endif
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/* we compute the CPU state. We assume it will not
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change during the whole generated block. */
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/* we compute the CPU state. We assume it will not
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change during the whole generated block. */
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#if defined(TARGET_I386)
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flags = env->segs[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
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flags |= env->segs[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
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flags |= (((unsigned long)env->segs[R_DS].base |
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(unsigned long)env->segs[R_ES].base |
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(unsigned long)env->segs[R_SS].base) != 0) <<
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GEN_FLAG_ADDSEG_SHIFT;
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if (!(env->eflags & VM_MASK)) {
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flags |= (env->segs[R_CS].selector & 3) << GEN_FLAG_CPL_SHIFT;
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} else {
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/* NOTE: a dummy CPL is kept */
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flags |= (1 << GEN_FLAG_VM_SHIFT);
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flags |= (3 << GEN_FLAG_CPL_SHIFT);
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}
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flags |= (env->eflags & (IOPL_MASK | TF_MASK));
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cs_base = env->segs[R_CS].base;
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pc = cs_base + env->eip;
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flags = (env->segs[R_CS].flags & DESC_B_MASK)
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>> (DESC_B_SHIFT - GEN_FLAG_CODE32_SHIFT);
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flags |= (env->segs[R_SS].flags & DESC_B_MASK)
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>> (DESC_B_SHIFT - GEN_FLAG_SS32_SHIFT);
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flags |= (((unsigned long)env->segs[R_DS].base |
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(unsigned long)env->segs[R_ES].base |
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(unsigned long)env->segs[R_SS].base) != 0) <<
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GEN_FLAG_ADDSEG_SHIFT;
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if (!(env->eflags & VM_MASK)) {
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flags |= (env->segs[R_CS].selector & 3) << GEN_FLAG_CPL_SHIFT;
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} else {
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/* NOTE: a dummy CPL is kept */
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flags |= (1 << GEN_FLAG_VM_SHIFT);
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flags |= (3 << GEN_FLAG_CPL_SHIFT);
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}
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flags |= (env->eflags & (IOPL_MASK | TF_MASK));
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cs_base = env->segs[R_CS].base;
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pc = cs_base + env->eip;
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#elif defined(TARGET_ARM)
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flags = 0;
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cs_base = 0;
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pc = (uint8_t *)env->regs[15];
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flags = 0;
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cs_base = 0;
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pc = (uint8_t *)env->regs[15];
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#else
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#error unsupported CPU
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#endif
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tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
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flags);
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if (!tb) {
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spin_lock(&tb_lock);
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/* if no translated code available, then translate it now */
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tb = tb_alloc((unsigned long)pc);
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tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
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flags);
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if (!tb) {
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/* flush must be done */
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tb_flush();
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/* cannot fail at this point */
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spin_lock(&tb_lock);
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/* if no translated code available, then translate it now */
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tb = tb_alloc((unsigned long)pc);
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/* don't forget to invalidate previous TB info */
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ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
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T0 = 0;
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}
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tc_ptr = code_gen_ptr;
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tb->tc_ptr = tc_ptr;
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tb->cs_base = (unsigned long)cs_base;
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tb->flags = flags;
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ret = cpu_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
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if (!tb) {
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/* flush must be done */
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tb_flush();
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/* cannot fail at this point */
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tb = tb_alloc((unsigned long)pc);
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/* don't forget to invalidate previous TB info */
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ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
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T0 = 0;
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}
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tc_ptr = code_gen_ptr;
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tb->tc_ptr = tc_ptr;
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tb->cs_base = (unsigned long)cs_base;
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tb->flags = flags;
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ret = cpu_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
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#if defined(TARGET_I386)
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/* XXX: suppress that, this is incorrect */
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/* if invalid instruction, signal it */
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if (ret != 0) {
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/* NOTE: the tb is allocated but not linked, so we
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can leave it */
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spin_unlock(&tb_lock);
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raise_exception(EXCP06_ILLOP);
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}
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/* XXX: suppress that, this is incorrect */
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/* if invalid instruction, signal it */
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if (ret != 0) {
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/* NOTE: the tb is allocated but not linked, so we
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can leave it */
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spin_unlock(&tb_lock);
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raise_exception(EXCP06_ILLOP);
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}
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#endif
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*ptb = tb;
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tb->hash_next = NULL;
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tb_link(tb);
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code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
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spin_unlock(&tb_lock);
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}
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*ptb = tb;
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tb->hash_next = NULL;
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tb_link(tb);
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code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
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spin_unlock(&tb_lock);
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}
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#ifdef DEBUG_EXEC
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if (loglevel) {
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fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
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(long)tb->tc_ptr, (long)tb->pc,
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lookup_symbol((void *)tb->pc));
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}
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if (loglevel) {
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fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
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(long)tb->tc_ptr, (long)tb->pc,
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lookup_symbol((void *)tb->pc));
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}
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#endif
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#ifdef __sparc__
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T0 = tmp_T0;
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T0 = tmp_T0;
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#endif
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/* see if we can patch the calling TB. XXX: remove TF test */
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if (T0 != 0
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#if defined(TARGET_I386)
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&& !(env->eflags & TF_MASK)
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#endif
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) {
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spin_lock(&tb_lock);
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tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
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spin_unlock(&tb_lock);
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}
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tc_ptr = tb->tc_ptr;
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/* see if we can patch the calling TB. XXX: remove TF test */
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#ifndef RING0_HACKS
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/* execute the generated code */
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gen_func = (void *)tc_ptr;
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#if defined(__sparc__)
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__asm__ __volatile__("call %0\n\t"
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"mov %%o7,%%i0"
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: /* no outputs */
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: "r" (gen_func)
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: "i0", "i1", "i2", "i3", "i4", "i5");
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#elif defined(__arm__)
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asm volatile ("mov pc, %0\n\t"
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".global exec_loop\n\t"
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"exec_loop:\n\t"
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: /* no outputs */
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: "r" (gen_func)
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: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
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#else
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gen_func();
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if (T0 != 0
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#if defined(TARGET_I386)
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&& !(env->eflags & TF_MASK)
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#endif
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) {
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spin_lock(&tb_lock);
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tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
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spin_unlock(&tb_lock);
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}
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#endif
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tc_ptr = tb->tc_ptr;
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/* execute the generated code */
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gen_func = (void *)tc_ptr;
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#if defined(__sparc__)
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__asm__ __volatile__("call %0\n\t"
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"mov %%o7,%%i0"
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: /* no outputs */
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: "r" (gen_func)
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: "i0", "i1", "i2", "i3", "i4", "i5");
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#elif defined(__arm__)
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asm volatile ("mov pc, %0\n\t"
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".global exec_loop\n\t"
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"exec_loop:\n\t"
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: /* no outputs */
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: "r" (gen_func)
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: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
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#else
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gen_func();
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#endif
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}
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} else {
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}
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}
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ret = env->exception_index;
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} /* for(;;) */
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#if defined(TARGET_I386)
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/* restore flags in standard format */
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@ -348,11 +399,11 @@ void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
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SegmentCache *sc;
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selector &= 0xffff;
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sc = &env->segs[seg_reg];
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/* NOTE: in VM86 mode, limit and seg_32bit are never reloaded,
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/* NOTE: in VM86 mode, limit and flags are never reloaded,
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so we must load them here */
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sc->base = (void *)(selector << 4);
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sc->limit = 0xffff;
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sc->seg_32bit = 0;
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sc->flags = 0;
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sc->selector = selector;
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} else {
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load_seg(seg_reg, selector, 0);
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@ -398,6 +449,8 @@ void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
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#include <signal.h>
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#include <sys/ucontext.h>
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#if defined(TARGET_I386)
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/* 'pc' is the host PC at which the exception was raised. 'address' is
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the effective address of the memory exception. 'is_write' is 1 if a
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write caused the exception and otherwise 0'. 'old_set' is the
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@ -407,42 +460,53 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
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{
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TranslationBlock *tb;
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int ret;
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uint32_t found_pc;
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#ifdef RING0_HACKS
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env = global_env; /* XXX: find a better solution */
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#endif
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#if defined(DEBUG_SIGNAL)
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printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n",
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printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
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pc, address, is_write, *(unsigned long *)old_set);
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#endif
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/* XXX: locking issue */
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if (is_write && page_unprotect(address)) {
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return 1;
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}
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/* see if it is an MMU fault */
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ret = cpu_x86_handle_mmu_fault(env, address, is_write);
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if (ret < 0)
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return 0; /* not an MMU fault */
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if (ret == 0)
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return 1; /* the MMU fault was handled without causing real CPU fault */
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/* now we have a real cpu fault */
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tb = tb_find_pc(pc);
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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ret = cpu_search_pc(tb, &found_pc, pc);
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if (ret < 0)
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return 0;
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#if defined(TARGET_I386)
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env->eip = found_pc - tb->cs_base;
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env->cr[2] = address;
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/* we restore the process signal mask as the sigreturn should
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do it (XXX: use sigsetjmp) */
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sigprocmask(SIG_SETMASK, old_set, NULL);
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raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1));
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cpu_restore_state(tb, env, pc);
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}
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#if 0
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printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
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env->eip, env->cr[2], env->error_code);
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#endif
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/* we restore the process signal mask as the sigreturn should
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do it (XXX: use sigsetjmp) */
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sigprocmask(SIG_SETMASK, old_set, NULL);
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raise_exception_err(EXCP0E_PAGE, env->error_code);
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/* never comes here */
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return 1;
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}
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#elif defined(TARGET_ARM)
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env->regs[15] = found_pc;
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/* XXX: do more */
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static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
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int is_write, sigset_t *old_set)
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{
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/* XXX: do more */
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return 0;
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}
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#else
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#error unsupported target CPU
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#endif
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/* never comes here */
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return 1;
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} else {
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return 0;
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}
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}
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#if defined(__i386__)
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@ -570,6 +634,6 @@ int cpu_signal_handler(int host_signum, struct siginfo *info,
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#else
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#error CPU specific signal handler needed
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#error host CPU specific signal handler needed
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#endif
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